Quantinuum H2 Quantum Processor

Updated 22 November 2025

Quantinuum’s H2 is a trapped-ion quantum processor featuring a 56-qubit QCCD architecture with dynamic ion shuttling for all-to-all connectivity.
It achieves high fidelity through rapid single- and two-qubit gates, integrated mid-circuit feedback, and advanced error correction protocols.
H2 enables scalable quantum simulations and advantage tasks by executing deeply entangled circuits beyond the reach of classical simulation techniques.

Quantinuum’s H2 Quantum Processor is a fully programmable, scalable trapped-ion quantum computing platform engineered for high-fidelity universal quantum operations. It features all-to-all qubit connectivity via dynamic ion shuttling, supports advanced quantum error correction (QEC) protocols, and achieves two-qubit gate fidelities needed for the execution of deeply entangling circuits at volume and depth beyond the practical reach of classical simulation tools. H2’s architecture, hardware primitives, and software layers enable experimental exploration from fault-tolerant logical qubit manipulation to quantum advantage tasks, making it a reference point for current and near-term quantum algorithms.

1. Hardware Architecture

The H2 processor employs a quantum charge-coupled device (QCCD) architecture based on segmented linear Paul traps, most recently realized as a 56-qubit system with a monolithic surface-electrode design (Gharibyan et al., 29 Oct 2025, Haghshenas et al., 26 Mar 2025). Qubits are stored in hyperfine “clock” states of ^{171}Yb⁺ ions, with sympathetic cooling mediated by interspersed ^{138}Ba⁺ ions (Ryan-Anderson et al., 25 Apr 2024, Hong et al., 4 Jun 2024). The trap is partitioned into four independent “gate zones,” where ions are moved mechanically through precise control of electrode voltages, allowing any pair of ions to be co-located for gate operations. This shuttling enables effective all-to-all qubit connectivity with the ability to realize circuit graphs that would otherwise be highly nonlocal.

Coherence times exceed 1 s (T_2^*), with T_1 limited by optical pumping to ≫100 s (Hong et al., 4 Jun 2024). Gates are implemented using stimulated Raman beams, focused into each interaction zone. Typical single-qubit gate times are on the order of 1–10 μs, and two-qubit gates require ≈100–200 μs (Haghshenas et al., 26 Mar 2025, Hong et al., 4 Jun 2024). State preparation and measurement (SPAM) is performed via state-dependent fluorescence with errors ∼2×10^{-3}.

2. Native Gate Set, Control, and Fidelity Metrics

H2’s native gate set includes arbitrary single-qubit rotations and two-qubit Ising-type entangling gates. Specifically, R_{ZZ}(θ)=\exp[–i (θ/2) Z⊗Z] is implemented via an effective Mølmer–Sørensen XX interaction compiled into an R_{ZZ}, with complete parallelization possible across all available gate zones (Haghshenas et al., 26 Mar 2025, Gharibyan et al., 29 Oct 2025). Typical gate fidelities are:

Operation	Fidelity (Best-Reported)	Error/Duration
Single-qubit gate	>99.99%	≲3×10^{-5}; ~10 μs
Two-qubit R_{ZZ}	99.94(1)%	~1.4–2×10^{-3}; ~100–200 μs
SPAM	>99.5%	~2×10^{-3}

For circuits up to 2240 two-qubit gates and 56 qubits (“circuit volume” ≳10^5), H2 maintains observable signal with error-mitigation (Haghshenas et al., 26 Mar 2025). Leakage errors and memory errors (dephasing, Z-rotation drift) are countered by mid-circuit leakage detection, dynamical decoupling, randomized compiling, zero-noise extrapolation (ZNE), and other custom protocols, holding total observable error to ≲5% even at depth (Haghshenas et al., 26 Mar 2025).

3. Connectivity and Logical Qubit Control

All-to-all connectivity is achieved by dynamic shuttling of qubits between four independent gate zones. Any two ions can interact directly, without SWAP overhead, removing planar embedding constraints and enabling nonlocal quantum codes and lattice operations (Hong et al., 4 Jun 2024). This approach permits the implementation of non-planar QEC codes with long-range stabilizers, such as the [[25,4,3]] Tanner-transformed surface code and the planar [[7,1,3]] color code (Steane code) (Ryan-Anderson et al., 25 Apr 2024, Hong et al., 4 Jun 2024).

Logical operations—including transversal gates, lattice surgery, and syndrome extraction—can be performed with real-time feedback. Mid-circuit measurement with crosstalk <10^{-4} and active qubit reset enable repeated rounds of syndrome extraction and fast Pauli correction. Real-time decoders (e.g., look-up-table) interpret measurement outcomes and drive adaptive feedback (Ryan-Anderson et al., 25 Apr 2024).

H2’s domain-specific logical programming layer (SLR, “Editor’s term”) composes error-correction primitives and directly compiles them to ion-transport and pulse sequences (Ryan-Anderson et al., 25 Apr 2024). This integration of hardware and logical abstraction is central to fault-tolerant experiments.

4. Error Correction and Fault Tolerance

In Steane code experiments, logical teleportation circuits with or without mid-circuit error correction (“0 QEC” and “1 QEC”) reach process fidelities F_p=0.989(2) and 0.975(2), respectively. Lattice-surgery teleportation achieves F_p=0.851(9) to 0.887(7). Postselection for error detection pushes fidelities above 0.99 (Ryan-Anderson et al., 25 Apr 2024).

The enablers are (a) high-fidelity entangling gates with error ≲2×10^{-3}, (b) rapid parallel gate and measurement, (c) real-time feedback decoding and Pauli correction, and (d) device-scale logical block composition with minimal local connectivity constraints (Ryan-Anderson et al., 25 Apr 2024, Hong et al., 4 Jun 2024).

5. Large-Scale Quantum Algorithms and Quantum Advantage

underpins demonstrations in quantum advantage benchmarks, digital quantum simulation, and hybrid quantum–classical algorithms. Key results include:

Heuristic Quantum Advantage: HQAP circuits with 56 qubits and up to 2000 two-qubit gates are executed in <2 hours, planting a δ=0.1 amplitude peak in the output that is verifiable via massive circuit sampling (Gharibyan et al., 29 Oct 2025). State-of-the-art classical simulation (tensor networks, Pauli path, belief propagation) is projected to require years on exascale systems for the same instance, suggesting an exponential scaling gap.
Quantum Simulation: In 56-qubit digitized Ising model experiments, circuits up to 2240 two-qubit gates are run, with evidence for Floquet prethermalization and emergent diffusive hydrodynamics (Haghshenas et al., 26 Mar 2025). These are not accessible to leading classical techniques even with large bond dimensions (MPS χ=4000).
Knot Invariants (Jones Polynomial): H2-2 is used for additive-error evaluation of the Jones polynomial at the fifth root of unity, exploiting efficient braid circuit compilation and symmetry-based error mitigation. Hardware runs reach ε_rel ≈ 40–70% at moderate depth on 16 qubits; extrapolation to 50–100 qubits and ≳2000 gates predicts quantum advantage for both runtime and energy (Laakkonen et al., 7 Mar 2025).
Quantum Chemistry and Error Mitigation: Early VQE studies on H2-class hardware demonstrate ground-state and excited-state calculation for H₂ with chemical accuracy, leveraging shallow circuits and error mitigation via quantum subspace expansion (QSE) (Colless et al., 2017).

6. Key Architectural and Methodological Innovations

Several core innovations distinguish H2:

Quantum Charge-Coupled Device (QCCD): Segmented trapping enables dynamic reconfiguration and all-to-all logic for scalable quantum circuits (Ryan-Anderson et al., 25 Apr 2024, Hong et al., 4 Jun 2024).
Fast, Adaptive Quantum Feedback: Mid-circuit measurement with low crosstalk, fast reset, and immediate correction enables deep QEC cycles, essential for break-even logical qubits and low-latency quantum algorithms (Ryan-Anderson et al., 25 Apr 2024).
Software-Defined Logical Layer (SLR): Logical qubit operations, lattice surgery, and code primitives are programmatically mapped to physical transport and gates by a dedicated compiler (Ryan-Anderson et al., 25 Apr 2024).
Error-Mitigation and Benchmarking Toolset: Protocols including zero-noise extrapolation, dynamical decoupling, randomized compiling, and algorithm-specific symmetry postselection allow reliable extraction of physical observables deep into circuit depth (Haghshenas et al., 26 Mar 2025, Laakkonen et al., 7 Mar 2025).
Complexity-Theoretic Insights: Hardness proofs for HQAP circuits demonstrate QCMA-completeness for peakedness detection, setting boundary conditions for both black-box quantum and classical algorithms (Gharibyan et al., 29 Oct 2025).

7. Applications and Scaling Outlook

H2’s current performance has established new domain benchmarks in QEC, digital quantum simulation, and verifiable quantum advantage. The system supports up to N=56 fully programmable qubits and all-to-all R_{ZZ} entangling gates, with circuit depths >2000. Its rapid hardware and feedback cycle times and software-abstracted logical control have enabled first-of-kind demonstrations:

Logical QEC exceeding break-even and multi-qubit syndrome cycling (Hong et al., 4 Jun 2024, Ryan-Anderson et al., 25 Apr 2024)
Quantum simulation of prethermal and hydrodynamic quantum matter at volumes beyond classical tractability (Haghshenas et al., 26 Mar 2025)
Benchmarking of classically intractable HQAP circuits (Gharibyan et al., 29 Oct 2025)
Knot-theoretic quantum invariants and chemical spectrum calculations with error mitigation (Laakkonen et al., 7 Mar 2025, Colless et al., 2017)

Further scale-up is expected to target 100+ qubits, drive deeper circuits via improved parallelization, and activate denser QEC codes as higher-fidelity benchmarks are achieved. The modular QCCD architecture and programmatic logical layer position H2 to serve as a reference system for QEC, algorithms research, and demonstrations of quantum advantage as classical boundaries are further pressed.