GENIE-ASI: Instruction to Identify Analog Subcircuits
- GENIE-ASI is a training-free, LLM-based method that identifies analog subcircuits from flattened SPICE netlists using a two-phase instruction-to-code approach.
- It employs few-shot natural-language induction followed by Python code synthesis to convert identification procedures into executable subcircuit parsers.
- The methodology is benchmarked on operational amplifiers, demonstrating competitive device-level results and challenges at complex stage-level identification.
GENIE-ASI, short for “Generative Instruction and Executable Code for Analog Subcircuit Identification,” is a training-free methodology for identifying analog subcircuits directly from flattened SPICE netlists. It uses LLMs in two phases: few-shot, in-context induction of natural-language identification procedures, followed by translation of those procedures into executable Python that parses unseen netlists and returns identified subcircuits. The method is positioned as the first training-free, LLM-based approach to analog subcircuit identification, and is introduced together with a dedicated operational-amplifier benchmark spanning device-, structure-, and stage-level labels (Pham et al., 26 Aug 2025).
1. Problem setting and motivation
Analog subcircuit identification is the task of locating canonical building blocks such as differential pairs, current mirrors, inverters, bias or load networks, and stages within flat SPICE netlists. In analog design automation, this task is foundational because it enables simulation and sizing workflows that operate on coherent device groups, supports layout synthesis and migration through matching and symmetry constraints, and contributes to topology synthesis, abstraction, equivalence checking, and functional reuse.
GENIE-ASI is motivated by the limitations of three established families of approaches. Human-curated rule systems and subcircuit libraries require substantial domain expertise, are costly to maintain, and are brittle under topological variation. Supervised machine learning, often based on graph neural networks, depends on large labeled corpora even though device-level annotation is expensive and distribution shift is common. Pattern matching through subgraph isomorphism can be accurate for explicitly enumerated templates, but it scales poorly and is inflexible when abstractions such as cascoding or folded structures are present. The GENIE-ASI proposal addresses this setting by replacing handcrafted template enumeration or large-scale supervision with a small number of demonstrations and an instruction-to-code synthesis pipeline (Pham et al., 26 Aug 2025).
2. Methodological core
The method is organized into two phases. In the first phase, an LLM observes a few labeled examples and induces step-by-step natural-language procedures for identifying a target subcircuit class across SPICE netlists. These procedures encode connection rules, grouping constraints, and handling of topological variants. In the second phase, the LLM translates the resulting instructions into executable Python, including assertions, so that the code can parse unseen netlists and output identified subcircuits.
A central design choice is the use of natural-language instructions as an intermediate representation. This layer is interpretable, can support human-in-the-loop refinement, and is reusable across models. A second design choice is that code is generated once per subcircuit type and then reused for subsequent inference without further LLM calls. A third design choice is strict training-free operation: the methodology relies on a handful of demonstrations rather than fine-tuning.
The input format is a flattened SPICE netlist with anonymized internal net names such as a, b, and c, a choice intended to reduce leakage and improve token efficiency. The paper uses a small labeled demonstration set with . MOSFETs are represented as flat SPICE lines of the form m<name> <drain> <gate> <source> <bulk> <model>, and capacitors as c<name> <n1> <n2>. The generated Python constructs typed device objects, distinguishes nmos and pmos, and performs pattern logic over device attributes and net connectivity (Pham et al., 26 Aug 2025).
3. Prompting pipeline, code synthesis, and identification logic
Instruction synthesis begins with Prompt #1, which asks the LLM to infer a step-by-step identification procedure for a given subcircuit from a labeled example. Prompt #2 then merges instruction sets from different examples to consolidate them and reduce duplication while preserving procedural consistency. The same LLM is used for both stages.
Code synthesis begins with Prompt #3, which translates the consolidated instructions into a Python function, findSubCircuit, that parses a netlist and returns identified instances. This prompt includes one labeled test netlist and its ground truth, and it requires assertions so that execution can be validated automatically. If those assertions fail, Prompt #4 supplies the error messages back to the LLM, which revises the code. The repair loop continues until assertions pass or a retry limit is reached; the reported maximum is five repairs. Passing code is added to a shared codebase, partially correct code with valid output formatting may be retained cautiously, and persistent syntax failures are discarded. Across an experiment, the full workflow uses up to 17 API calls per LLM, approximately six for instruction generation, five for instruction merging, and up to six for code generation and repair.
The identification logic is hierarchical. At HL1, the method targets device-level motifs such as diode-connected MOSFETs, load capacitors, and compensation capacitors. For example, diode-connected devices are detected through gate==drain, load capacitors are identified as output-to-ground, and compensation capacitors as output-to-internal or internal-to-internal. At HL2, the method identifies structure-level motifs including current mirrors, differential pairs, and inverter variants. Current mirrors are grouped by transistor type and shared gate, filtered by shared source and bulk, required to contain at least one diode-connected device, and extended to cascoded or multi-stage forms by reasoning over source-drain stacking and shared bias nets. Differential pairs are tied to input-driven gates and common-source structure, while inverter identification relies on analog inverter topology, gate coupling, and complementary pull-up or pull-down checks. At HL3, the method addresses stage-level partitions such as firstStage, secondStage, thirdStage, feedBack, loadPart, and biasPart, using signal-flow reasoning from inputs to outputs and back through feedback paths (Pham et al., 26 Aug 2025).
4. Benchmark design and evaluation protocol
To evaluate LLM-based approaches systematically, the work introduces a benchmark built atop ACST, integrating FUBOCO synthesis and rule-based annotation. The full generation process yields approximately 47,000 flattened operational-amplifier netlists, from which 300 representative netlists are curated for evaluation because of token and cost constraints. The benchmark is balanced by size: 100 small circuits with fewer than 20 transistors, 100 medium circuits with 20–30 transistors, and 100 large circuits with more than 30 transistors. It also spans one-stage, two-stage, and three-stage op-amps, including symmetric, single-ended, and fully differential forms.
| Hierarchy level | Labels | Scope |
|---|---|---|
| HL1 | MosfetDiode, load_cap, compensation_cap |
Device-level |
| HL2 | DiffPair, CM, Inverter with 18 variants |
Structure-level |
| HL3 | firstStage, secondStage, thirdStage, feedBack, loadPart, biasPart |
Stage-level |
The benchmark statistics illustrate the scale of annotation. Across the 300 circuits, HL1 includes 1952 diode-connected MOSFETs, 385 load capacitors, and 405 compensation capacitors. HL2 includes 1884 simple current mirrors, 279 Improved Wilson mirrors, 39 Wilson mirrors, 126 cascode current mirrors, 52 wide-swing cascode current mirrors, and 405 differential pairs; nine inverter variants are also represented. HL3 labels are present across circuits with 300 firstStage, 268 secondStage, 104 thirdStage, 300 loadPart, 300 biasPart, and 85 feedBack instances.
Evaluation uses two complementary criteria. Under strict cluster-level evaluation, a prediction is correct only if both the label and the full cluster membership exactly match a ground-truth subcircuit. Under node-level classification, correctness is defined per transistor label while ignoring grouping. The reported metrics are precision, recall, and F1-score for either criterion. This distinction is important because stage-level identification can be partially right at the node level while failing strict cluster matching if even one device is omitted or added (Pham et al., 26 Aug 2025).
5. Empirical results and failure modes
The principal empirical pattern is a hierarchy-dependent degradation in performance as structural abstraction increases. On simple device-level structures, GENIE-ASI matches rule-based performance, with HL1 results reaching in simple settings and GPT‑4.1 strict HL1 F1 reported in the range of approximately $0.97$ to $1.0$. On moderate abstractions at HL2, the method remains competitive, with GPT‑4.1 achieving strict . On complex stage-level HL3 clusters, performance declines substantially, with GPT‑4.1 strict . The overall average strict F1 is reported as approximately $0.70$ for GPT‑4.1, $0.62$ for Grok 3 Beta, $0.61$ for Gemini 2.5, $0.48$ for Deepseek R1, 0 for Claude 3.7, 1 for LLaMA 3.3 70B, and approximately 2 for LLaMA 3 70B Instruct (Pham et al., 26 Aug 2025).
Across baselines, instruction-to-code generally outperforms direct prompting and instruction-following JSON outputs under strict cluster-level metrics. Direct code generation can be strong on node-level classification for some models, notably Gemini 2.5 and Claude 3.7, but instruction-derived code improves consistency and determinism for strict grouping tasks. The AnyGraph baseline, constrained to six demonstration graphs, performs poorly on node classification across hierarchy levels; an HL2 F1 of approximately 3 is reported, suggesting weak generalization under extremely small training sets.
The error analysis is structurally informative. HL3 failures are dominated by the difficulty of large, heterogeneous clusters such as biasPart and loadPart, where strict evaluation is unforgiving and any missed or extra device invalidates the entire cluster. Common confusions occur among firstStage, thirdStage, and loadPart, and feedBack is often identified only partially. At HL2, inverter identification lags current mirrors and differential pairs; some models over-identify inverter-like topologies when signal-path constraints should exclude them. Over-identification is especially visible in Deepseek R1, which tends to produce extra clusters and therefore lower precision, while GPT‑4.1 is described as more conservative and more aligned with the ground truth. On the code-generation side, assertion failures dominate syntax failures, and increasing the retry limit beyond five yields little benefit for HL3 (Pham et al., 26 Aug 2025).
6. Contributions, limitations, and research context
GENIE-ASI makes two direct contributions. First, it proposes what is described as the first training-free, LLM-based methodology for analog subcircuit identification from flattened SPICE netlists, built around instruction induction, executable-code generation, and assertion-guided self-repair. Second, it contributes an evaluation-ready op-amp benchmark spanning 300 curated circuits, three hierarchy levels, and 18 HL2 variants. Taken together, these contributions suggest a shift in analog design automation from fixed rule libraries or data-hungry supervision toward reusable program synthesis driven by a small number of demonstrations.
The method also has explicit limitations. Performance on complex stage-level clusters remains weak, indicating that deeper structural reasoning and broader global context are still missing. Prompt quality matters, and the use of a single labeled example in Prompt #3, imposed by token and cost constraints, limits coverage of topological variants. Model variability is large; smaller instruction-following models can fail code repair entirely. Reproducibility is affected by stochastic generation even when assertions improve determinism. Computational cost is nontrivial because each experiment may require up to 17 API calls. The authors also note risks of hallucinated or unsafe code, mitigated but not eliminated by anonymization, assertions, and a discard policy.
Several future directions are identified. These include stronger graph reasoning in generated code through explicit netlist graphs, path tracing, dominance or frontier analysis, and multi-hop signal-path checks; retrieval augmentation with curated circuit snippets and variant catalogs; formal verification loops using property checks, SMT constraints, or netlist equivalence; larger and stronger models with structured generation; multi-example code prompts within token limits; and extension beyond op-amps to filters, comparators, and RF front-ends (Pham et al., 26 Aug 2025).
A recurrent source of confusion is nomenclature. The analog-design GENIE-ASI described here is unrelated to the world-model line of “Genie” research on interactive environments (Bruce et al., 2024, Kazemi et al., 2024), to the reference-guided instance-editing framework GENIE evaluated on the AnyInsertion dataset (Zhou et al., 17 Dec 2025), to GenIAS for time-series anomaly synthesis (Darban et al., 12 Feb 2025), or to GENIE as a novelty metric for generated text (Namuduri et al., 11 Jun 2026). In the analog-EDA setting, GENIE-ASI refers specifically to generative instruction and executable code for analog subcircuit identification.