Copy Subcircuit: Mechanisms and Applications

• Copy Subcircuit is a concept that defines the preservation and transfer of existing structures across domains such as transformer attention, text generation, and circuit design.
• It encompasses diverse methodologies, including phase transitions in attention models, supervised copy decisions in neural networks, analog feedback for memristor programming, and hierarchical subcircuit instantiation in EDA.
• Applications highlight critical trade-offs in performance and design, yielding improved accuracy in text generation, robust analog control, and efficient extraction of functional circuit modules.

Searching arXiv for recent and directly relevant papers on “copy subcircuit” across the senses represented in the source material. Searching for "copy subcircuit" on arXiv. “Copy subcircuit” is not a single universally standardized term; in current research usage it denotes several closely related technical ideas centered on transfer, reuse, or reproduction of structure. In transformer theory, it refers to the first-layer attention pattern of an induction head that implements shift-by-one copying, with target operator $G^\star_{ab} = \delta_{a-1,b}$ on the task $y_a(x)=x_{a-1}$ (Lavie et al., 10 Jun 2026). In neural text generation, it denotes the copy-decision component of a Pointer-Generator-style model, in which a scalar $p_{gen}$ controls mixture between vocabulary generation and source copying (Choi et al., 2021). In analog electronics, it denotes feedback circuits that copy the value of a conventional resistor into a memristive device (Merrikh-Bayat et al., 2013). In circuit CAD and simulation, related usage concerns reusable hierarchical subcircuit instantiation and the extraction or identification of functional subcircuits from flat SPICE netlists (Long et al., 2024, Pham et al., 26 Aug 2025). These usages are technically distinct, but they share the common motif of preserving or transferring an already existing value, token, or structural pattern.

1. Terminological scope and recurring abstraction

The term spans at least four research settings represented in the literature.

Domain	Meaning of “copy”
Transformer attention	Shift-by-one attention pattern in an induction-head setting
Neural text generation	Source-token copying controlled by a supervised switch
Memristive circuits	Programming a memristor so $R_{\mathrm{mem}}=R_{\mathrm{ref}}$
Circuit simulation and EDA	Reuse, instantiation, or extraction of subcircuit structure

In the attention setting, the copied object is a token continuation associated with a previous occurrence of the same context token. In supervised sequence generation, the copied object is a source-side word selected instead of a vocabulary item. In the memristive setting, the copied object is an analog resistance value rather than a symbolic token. In hierarchical circuit simulation and analog design automation, the copied object is a module definition or a functional grouping of devices that is reused, instantiated, or recovered from a netlist [(Lavie et al., 10 Jun 2026); (Choi et al., 2021); (Merrikh-Bayat et al., 2013); (Long et al., 2024); (Pham et al., 26 Aug 2025)].

This suggests that “copy subcircuit” functions less as a domain-specific primitive than as a family resemblance across mechanisms that preserve an external referent under architectural or algorithmic constraints.

2. Attention-theoretic copy subcircuits in induction heads

In the transformer literature represented by “Phase Transitions in Attention: A Bayesian Theory of Copy Head Emergence” (Lavie et al., 10 Jun 2026), the copy subcircuit is the first-layer attention pattern of an induction head that implements shift-by-one copying. The canonical example is

$[\dots, A, B, \dots, A] \to B,$

and the simplified supervised task is

$y_a(x)=x_{a-1},$

with periodic boundary conditions. The corresponding ideal attention pattern is the shift-by-one operator

$G^\star_{ab} = \delta_{a-1,b}.$

The analyzed model is a single-layer, single-head attention network on one-hot sequences $x_a \in \{0,1\}^V$, with hidden state

$h_a = w_{\mathrm{emb}} x_a + p_a,$

pre-softmax score matrix

$G_{ab} = h_a^\top W_G h_b,$

and, for softmax attention,

$y_a(x)=x_{a-1}$0

The paper treats the attention matrix $y_a(x)=x_{a-1}$1 as the macroscopic variable and derives a closed-form posterior

$y_a(x)=x_{a-1}$2

Its effective action contains likelihood terms and prior terms, formalizing competition between data fit and structural simplicity (Lavie et al., 10 Jun 2026).

A central result is a low-dimensional reduction

$y_a(x)=x_{a-1}$3

where $y_a(x)=x_{a-1}$4 measures uniform pooling and $y_a(x)=x_{a-1}$5 measures copying. In linear attention, the emergence of the copy subcircuit proceeds through a second-order phase transition into a uniform pooling phase, followed by a smooth crossover toward copying. In softmax attention, the posterior becomes effectively one-dimensional in the copy direction, develops two competing minima, and exhibits a first-order phase transition at a critical training-set size $y_a(x)=x_{a-1}$6, with a discontinuous jump in the order parameter and a sharp loss drop (Lavie et al., 10 Jun 2026).

The paper’s interpretation is that the copy subcircuit is the minimal circuit needed for induction heads and related in-context learning behaviors. A plausible implication is that abrupt capability acquisition in softmax transformers can arise from the geometry of the attention posterior rather than from gradual local feature accumulation alone.

3. Supervised copy subcircuits in neural sequence generation

In “May the Force Be with Your Copy Mechanism: Enhanced Supervised-Copy Method for Natural Language Generation” (Choi et al., 2021), the copy subcircuit is the copy-decision component inside a Pointer-Generator-style architecture. At decoder timestep $y_a(x)=x_{a-1}$7, the model computes an attention distribution $y_a(x)=x_{a-1}$8, a vocabulary distribution $y_a(x)=x_{a-1}$9, and a scalar soft switch $p_{gen}$0. The final token distribution is

$p_{gen}$1

The paper does not replace this generator-copy mixture. Instead, it adds explicit supervision for $p_{gen}$2 and retains ordinary generation loss. The full timestep loss is

$p_{gen}$3

with

$p_{gen}$4

and

$p_{gen}$5

Two supervision variants are defined. In force-copy, if the gold target word $p_{gen}$6 appears in the source $p_{gen}$7, the switch is trained with

$p_{gen}$8

and otherwise with

$p_{gen}$9

In force-copy-unk, copying is forced only when the gold target word is both in the source and not in the target vocabulary $R_{\mathrm{mem}}=R_{\mathrm{ref}}$0 (Choi et al., 2021).

The model therefore uses two signals as supervision: source-sequence membership and target-vocabulary membership. The source identifies copy-candidates; the vocabulary boundary determines whether a source-overlapping token should still be generated rather than copied. The paper explicitly retains $R_{\mathrm{mem}}=R_{\mathrm{ref}}$1 even when copying is forced, arguing against weakening vocabulary learning.

Empirically, the work reports improved copying quality and distinct copy–generate tradeoffs. On CNN/DailyMail, Copy Precision is reported as 47.80% for Pointer-Generator, 47.81% for force-copy, and 48.84% for force-copy-unk. Human evaluation reports force-copy as best for readability and factuality, and force-copy-unk as best for abstractness. On structured data generation, force-copy and force-copy-unk achieve the highest RG precision among neural models on ROTOWIRE and MLB, and force-copy-unk reaches RG precision comparable to gold on ROTOWIRE (Choi et al., 2021).

In this usage, the “subcircuit” is not a hardware block but a trainable decision module embedded inside a larger generative system. Its technical role is to regulate when reproduction of source material should dominate over lexical generation.

4. Memristive copy circuits as analog resistance-programming loops

In “Circuit proposition for copying the value of a resistor into a memristive device supported by HSPICE simulation” (Merrikh-Bayat et al., 2013), copying is literal analog-state transfer: the goal is to set the memristance of a device equal to a desired resistor value $R_{\mathrm{mem}}=R_{\mathrm{ref}}$2. The paper proposes two simple feedback circuits that automatically tune a memristor’s resistance until it matches a reference resistor, thereby avoiding trial-and-error programming.

The operating principle is a closed-loop comparator-like feedback structure composed of a reference resistor, two equal resistors $R_{\mathrm{mem}}=R_{\mathrm{ref}}$3, an op-amp, the memristor, and an op-amp supply voltage $R_{\mathrm{mem}}=R_{\mathrm{ref}}$4. Because the memristor is treated as asymmetric, one terminal polarity tends to decrease resistance and the opposite polarity tends to increase resistance. Two circuits are therefore required: one for increasing memristance when $R_{\mathrm{mem}}=R_{\mathrm{ref}}$5, and one for decreasing memristance when $R_{\mathrm{mem}}=R_{\mathrm{ref}}$6 (Merrikh-Bayat et al., 2013).

For the increase-resistance circuit, the divider relation is

$R_{\mathrm{mem}}=R_{\mathrm{ref}}$7

Initially, if $R_{\mathrm{mem}}=R_{\mathrm{ref}}$8, then

$R_{\mathrm{mem}}=R_{\mathrm{ref}}$9

the op-amp output saturates high, and the memristor is driven in the polarity that increases its resistance. The process continues until

$[\dots, A, B, \dots, A] \to B,$0

which corresponds to

$[\dots, A, B, \dots, A] \to B,$1

The paper states the steady-state condition as

$[\dots, A, B, \dots, A] \to B,$2

The device equations are given in both general and specific forms: $[\dots, A, B, \dots, A] \to B,$3 and, for the idealized current-controlled memristor,

$[\dots, A, B, \dots, A] \to B,$4

The HP-memristor model is

$[\dots, A, B, \dots, A] \to B,$5

with state evolution

$[\dots, A, B, \dots, A] \to B,$6

and window function

$[\dots, A, B, \dots, A] \to B,$7

The HSPICE implementation uses the Biolek-style HP memristor subcircuit with parameters $[\dots, A, B, \dots, A] \to B,$8, $[\dots, A, B, \dots, A] \to B,$9, $y_a(x)=x_{a-1},$0, $y_a(x)=x_{a-1},$1, $y_a(x)=x_{a-1},$2, $y_a(x)=x_{a-1},$3, $y_a(x)=x_{a-1},$4, op-amp AD711A, supply $y_a(x)=x_{a-1},$5, simulation interval $y_a(x)=x_{a-1},$6 to $y_a(x)=x_{a-1},$7, and timestep $y_a(x)=x_{a-1},$8 (Merrikh-Bayat et al., 2013).

Reported results are specific. For increasing resistance from $y_a(x)=x_{a-1},$9 to $G^\star_{ab} = \delta_{a-1,b}.$0, the memristance reaches steady state in about 7 ms, with a small steady-state error attributed to the finite timestep. When $G^\star_{ab} = \delta_{a-1,b}.$1, settling time increases to about 40 ms. For decreasing resistance from $G^\star_{ab} = \delta_{a-1,b}.$2 to $G^\star_{ab} = \delta_{a-1,b}.$3, $G^\star_{ab} = \delta_{a-1,b}.$4 and $G^\star_{ab} = \delta_{a-1,b}.$5 become equal in less than 6 ms (Merrikh-Bayat et al., 2013).

The paper explicitly notes several limitations: the first circuit cannot decrease memristance, the second is needed for downward programming, only the HP-memristor model is demonstrated, time-varying reference resistors are not studied, and a more compact transistor-level design is desirable. It also points toward a single universal circuit and copying resistance from one memristor to another as future directions (Merrikh-Bayat et al., 2013).

5. Copying as subcircuit reuse in hierarchical circuit simulation

A different but closely related meaning appears in “Computational Graph Representation of Equations System Constructors in Hierarchical Circuit Simulation” (Long et al., 2024). Here the relevant notion is not copying a value but copying a subcircuit definition through repeated hierarchical instantiation. The paper models hierarchical circuits as a computational graph over modules, explicitly analogizing subcircuit definitions to functions in programming languages.

The flat circuit equation system is written as

$G^\star_{ab} = \delta_{a-1,b}.$6

while hierarchical construction decomposes it into contributions

$G^\star_{ab} = \delta_{a-1,b}.$7

This recursive decomposition allows one subcircuit definition to be instantiated many times, each instance with its own node mapping and parameter bindings (Long et al., 2024).

The paper’s JSON netlist representation defines modules by external nodes, internal nodes, input parameters, a Schematic decomposition, and optionally a SubModel that computes intrinsic parameters. The SizeDepResistor example computes an intrinsic parameter $G^\star_{ab} = \delta_{a-1,b}.$8 from Rlength and Rwidth and passes it to a reusable lower-level resistor element. The execution algorithm EvalCompositeSubCkt assembles nodes, computes intrinsic parameters from current signals and input parameters, assembles parameters, recursively calls lower-layer subcircuits, evaluates basic elements, collects remainders, and backpropagates gradients through the hierarchy (Long et al., 2024).

Runtime parameter dependence is central. With external nodes en, internal nodes in, input parameters ip, global variables gv, constants c, and intrinsic parameters intrp,

$G^\star_{ab} = \delta_{a-1,b}.$9

$x_a \in \{0,1\}^V$0

and

$x_a \in \{0,1\}^V$1

The paper requires Jacobians

$x_a \in \{0,1\}^V$2

so gradients can propagate through hierarchical modules. For intrinsic-parameter backpropagation, if $x_a \in \{0,1\}^V$3,

$x_a \in \{0,1\}^V$4

The paper’s examples show this framework in both device modeling and optimization. A CMOS model uses “equivalent circuit decomposition + dynamic parameters,” with intrinsic parameters

$x_a \in \{0,1\}^V$5

and an operational amplifier auto-sizing problem is solved with 72 variables in a reported run time of 356 seconds including compilation and parsing overhead, using Ipopt (Long et al., 2024).

In this setting, “copy subcircuit” is best understood as structural reuse with instance-local parameterization and differentiable execution, rather than as value replication.

6. Extraction and identification of subcircuits from SPICE netlists

“GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification” (Pham et al., 26 Aug 2025) addresses the inverse problem: given a flattened SPICE netlist, recover the functional subcircuits embedded in it. The task is to recognize groups of devices corresponding to structures such as diode-connected transistors, current mirrors, differential pairs, inverters, amplification stages, load parts, and bias parts. In effect, the output is an extracted device set for each subcircuit class.

GENIE-ASI is training-free and operates in two phases. First, an LLM derives natural-language instructions for identifying a target subcircuit class: $x_a \in \{0,1\}^V$6 These are merged into a consolidated instruction set: $x_a \in \{0,1\}^V$7 Second, the instructions are translated into executable Python: $x_a \in \{0,1\}^V$8 If assertion tests fail, code repair is performed with

$x_a \in \{0,1\}^V$9

At inference time, the generated Python parses component lines, extracts device connections, groups candidates by shared nodes and device type, checks topological constraints such as gate-sharing, source sharing, and diode connections, and outputs the instance names belonging to each subcircuit. The method is therefore generative in rule discovery but algorithmic in final recognition (Pham et al., 26 Aug 2025).

The benchmark introduced in the paper contains 300 representative synthetic operational-amplifier netlists drawn from a broader synthesized pool of about 47,000 flattened SPICE netlists. It evaluates three hierarchy levels: HL1 device level, HL2 structure level, and HL3 stage level. Reported strict F1 values for GENIE-ASI with GPT-4.1 are

$h_a = w_{\mathrm{emb}} x_a + p_a,$0

with overall $h_a = w_{\mathrm{emb}} x_a + p_a,$1. The abstract also reports that the method matches rule-based performance on simple structures with F1-score $h_a = w_{\mathrm{emb}} x_a + p_a,$2, remains competitive on moderate abstractions with F1-score $h_a = w_{\mathrm{emb}} x_a + p_a,$3, and shows potential on complex subcircuits with F1-score $h_a = w_{\mathrm{emb}} x_a + p_a,$4 (Pham et al., 26 Aug 2025).

This literature does not use “copy subcircuit” as a formal label, but it operationalizes a closely related idea: identifying, extracting, and reusing functional blocks from textual circuit descriptions.

7. Formal analogues: copying as substitution, propagation, and model structure

A broader formal perspective emerges when these usages are compared with “Copy Propagation subsumes Constant Propagation” (S. et al., 2022). That paper is not about circuit modules, but it gives a generic definition of copy propagation in which a copy statement is any assignment

$h_a = w_{\mathrm{emb}} x_a + p_a,$5

where $h_a = w_{\mathrm{emb}} x_a + p_a,$6 is either a constant or a variable, represented as a pair $h_a = w_{\mathrm{emb}} x_a + p_a,$7. It then defines a forward data-flow analysis of Available Copy Statements using set-valued facts, intersection at control-flow joins,

$h_a = w_{\mathrm{emb}} x_a + p_a,$8

and transfer

$h_a = w_{\mathrm{emb}} x_a + p_a,$9

Transformation then performs recursive lookup so that copy chains can collapse in one pass (S. et al., 2022).

The direct subject matter differs from attention heads, memristor programming loops, and SPICE hierarchies. Nevertheless, the paper makes explicit a unifying abstraction: copy is not restricted to identity transfer between variables, but can be defined generically enough to include constant propagation as a special case. This suggests an analogous interpretive lens for the other literatures. In the attention case, the copied object is an offset token relation; in the seq2seq case, a source token; in the memristive case, a resistance value; in hierarchical simulation, a parameterized module body; and in netlist analysis, a functional device grouping. Across these domains, copying is characterized less by representational medium than by preservation of a source structure under controlled transformation (S. et al., 2022).

This interpretive commonality should not obscure the differences in mechanism. Attention-theoretic copy subcircuits are learned statistical operators. Supervised copy mechanisms in text generation are loss-shaped mixture components. Memristive copy circuits are closed-loop analog control systems. Hierarchical circuit “copying” is recursive module instantiation with runtime parameter passing. Netlist-level subcircuit identification is an extraction problem over flattened structural descriptions. The shared vocabulary is therefore real, but only partially uniform.