Event-Driven ADC: Principles & Applications

• Event-driven ADC converts analog signals into digital outputs only when significant events occur, enabling adaptive and efficient data capture.
• It employs methods like level-crossing, predictive triggering, and integrate-and-fire circuits to optimize power consumption and data compression.
• Applications include biomedical sensing, neuromorphic processing, and sparse signal recovery, demonstrating improved efficiency and performance.

Event-driven analog-to-digital conversion (ED-ADC) encompasses a class of methodologies and circuits that discretize analog signals into digital representations by generating quantized output only when salient “events” occur in the input waveform. Unlike classical clocked ADCs, which sample at uniform intervals regardless of signal content, event-driven architectures exploit nonuniform sampling strategies to maximize data efficiency, compress information, and reduce power in systems where signals are sparse or exhibit bursty dynamics. Event-driven ADC principles are foundational in modern neuromorphic engineering, low-power sensor frontends, and systems that must operate within strict bandwidth or energy budgets.

1. Fundamental Principles of Event-Driven ADC

Event-driven ADC architectures are governed by signal-dependent sampling policies, whereby the occurrence of a quantization event is triggered by the signal crossing a threshold, leaving a predictive region, or accumulating sufficient information over time. Prominent triggering mechanisms include:

• Level-Crossing and Delta Modulation: An event is generated when the analog input departs by at least Δ from its last quantized value, leading to nonuniformly spaced, data-proportional samples (Narayanan et al., 2023, Lakshmiramanan et al., 9 Apr 2026).
• Predictive/Window-Based Triggering: Quantization is performed only if the input escapes a dynamically formed window predicted from past samples (Tang et al., 2022).
• Time-Encoding Machines (TEMs): Event times are dictated by an integrate-and-reset circuit, where the area under the input (or its transformed version) must reach a fixed threshold before an event occurs (Naaman et al., 2023, Florescu et al., 2022).
• Modulo and Hysteretic Nonlinearities: A modulo operation folds excessive amplitude excursions to maintain bounded ranges, ensuring nonvanishing event density even for high-dynamic-range signals (Florescu et al., 2022).

These principles depart from uniform, clock-driven quantization by making event generation adaptive to the signal’s temporal and amplitude characteristics.

2. Core Circuit and System Architectures

Multiple circuit topologies have been reported for event-driven ADCs. Key elements include:

• Integrate-and-Fire Engines: A continuous or bandpass-filtered input is integrated until a threshold is reached, after which a comparator flags an event and a fast reset is performed. This mechanism underpins sub-Nyquist time-encoding machines (IF-TEMs) (Naaman et al., 2023), asynchronous sigma-delta modulators (ASDMs) (Florescu et al., 2022), and ADM-based spike encoders (Lakshmiramanan et al., 9 Apr 2026).
• Predictive Window Comparators: In Dynamic Predictive Sampling ADCs (DPS-ADC), prior two quantized outputs are used to forecast the next value. Thresholds create a “tracking window”; a mismatch between the predicted range and actual input invokes quantization and time-stamping (Tang et al., 2022).
• Multi-Channel Analog Front-Ends: Chips such as SPAIC integrate multiple identical event-driven channels, with programmable gain, filter characteristics, and threshold settings. Each channel feeds an asynchronous event packet (with address and polarity) into a shared output bus (Narayanan et al., 2023).
• Modulo-Hysteresis Blocks: To extend dynamic range, the input undergoes modulo and hysteretic transformations prior to event generation, avoiding saturation and ensuring sufficient sample density for high-amplitude signals (Florescu et al., 2022).

The circuit topologies are tailored to application-specific performance, area, energy, and integration constraints, favoring asynchronous and data-driven logic to minimize static and dynamic power.

3. Information Encoding and Event Representation

The conversion of analog signals into events in ED-ADC systems is marked by a shift from amplitude codewords at fixed times to timestamp-encoded, polarity-encoded, or phase-encoded digital outputs:

• Timestamped Events: Each event is tagged with its occurrence time and, when applicable, an amplitude code. For DPS-ADC, an event comprises a 10-bit quantization plus a 10-bit timestamp (Tang et al., 2022).
• Signed Spike Streams: In delta-modulation or ADM implementations, UP and DOWN (or ON/OFF) spikes indicate excursions above or below the previous value, forming a signed difference encoding (Lakshmiramanan et al., 9 Apr 2026, Narayanan et al., 2023).
• Phase- or Time-to-First-Spike (TTFS) Codes: In integrate-and-fire models with phase encoding, each analog sample window emits exactly one spike, whose timing encodes the original amplitude within that window (Lopez-Randulfe et al., 2023).
• Accumulated Area Encoding: TEM and ASDM structures associate each event with a specific increment in the analog variable’s integral, allowing direct inversion for reconstructing specific classes of signals (e.g., streams of Diracs or FRI signals) (Naaman et al., 2023, Florescu et al., 2022).

The representations thus produced are highly compressed, data-adaptive, and can be directly consumed by downstream digital or neuromorphic processors.

4. Signal Recovery, Performance Metrics, and Trade-Offs

Reconstruction algorithms and system-level trade-offs are dictated by the combination of event-encoding policy, threshold setting, and signal model:

• Data Compression and Rate Reduction: Compression factors up to 6.17× (measured for ECG on DPS-ADC at Δ=10 mV (Tang et al., 2022)) and 10× sub-Nyquist operation (for IF-TEM on FRI signals (Naaman et al., 2023)) are attainable, with events generated only where signal transitions/innovations occur.
• Power Efficiency: Event-driven architectures demonstrate substantial power savings—e.g., 31% for DPS-ADC compared to clocked SAR-ADC in continuous monitoring settings (Tang et al., 2022); ~800 nW/channel worst-case for SPAIC at 100 kHz (Narayanan et al., 2023); 60.73 nJ/spike for ADM (Lakshmiramanan et al., 9 Apr 2026); 150 μW system-level in MEDS (Florescu et al., 2022).
• Reconstruction Error: Signal fidelity is tied to the event threshold (Δ or δ), DAC and comparator accuracy, and decoding algorithm. For DPS-ADC, RMS error rises with Δ but remains below clinical thresholds for arrhythmia detection at Δ=10 mV (Tang et al., 2022). For IF-TEM encoding pulse streams, reconstruction yields –25 dB MSE (Naaman et al., 2023).
• Timing Resolution: ADC implementations utilizing event timestamps achieve resolutions of ≈10 bits (e.g., 1.48 μs in LIF phase encoders (Lopez-Randulfe et al., 2023); 1 ns for US-ADC (Florescu et al., 2022)).
• Dynamic Range Extension: MEDS extends input range by up to 20× compared to conventional sigma-delta ADCs, preserving error <1% for bandlimited signals (Florescu et al., 2022).

Trade-offs arise between event density (compression), reconstruction error, energy per event, and latency. Larger thresholds yield sparser events and greater data/power savings at the cost of higher error, with small thresholds reverting to near-classical behavior plus comparator overhead.

5. Application Domains and Implementation Results

ED-ADC is applied across a spectrum of fields, with measured silicon and prototype results demonstrating feasibility:

• Wearable and Biomedical Sensing: DPS-ADC in 0.18 μm CMOS targets energy-efficient ECG monitoring, recovers QRS, P-, and T-wave morphology for clinical diagnosis, and operates at 368 nW/channel (Tang et al., 2022).
• Brain–Machine Interfaces (BMIs): Asynchronous ADM-based frontends in 65 nm CMOS encode neural biopotentials as ON/OFF spikes, supporting SNN decoding at energy budgets of 60.73 nJ/spike, maintaining F1 ≈ 80% against behavioral models (Lakshmiramanan et al., 9 Apr 2026).
• General-Purpose Sensory Interfaces: SPAIC concatenates LNA, filter, and dual-mode encoders for edge-neuromorphic applications, enabling sub-μW/channel operation across 100 Hz–100 kHz (Narayanan et al., 2023).
• Time-Encoding of FRI and Sparse Signals: IF-TEM ADC hardware achieves near-perfect recovery of pulse delays/amplitudes for FRI signals at 10× below Nyquist, with explicit error analysis and sub-mm² ASIC feasibility (Naaman et al., 2023).
• High Dynamic Range Sensing: MEDS supports input excursions up to 20× base range with <1% error and 150 μW power (Florescu et al., 2022).
• Direct Neuromorphic Processing: LIF-based phase encoders allow one spike per sample with delay encoding, facilitating efficient spectral analysis via spiking FFT on platforms like SpiNNaker 2 (Lopez-Randulfe et al., 2023).

6. Signal Models, Decoding, and Algorithmic Guarantees

Several ED-ADC schemes leverage structured signal models and specialized decoding:

• Finite-Rate-of-Innovation (FRI) Signals: Time-encoding achieves sub-Nyquist performance by exploiting the low degrees of freedom (e.g., a stream of L Dirac pulses), with exact parameter recovery ensured for sufficient event density (Naaman et al., 2023).
• Bandlimited Recovery with MODULO: MEDS combines modulo folding and asynchronous integration to guarantee recovery under explicit event-rate bounds, with provable L² error decay under iterative local-average algorithms and geometric convergence with threshold tuning (Florescu et al., 2022).
• Predictive Algorithms: DPS-ADC windowing leverages second-order linear prediction for input signals modelled as smooth, low-sparsity waveforms such as ECG, balancing skip accuracy with information retention (Tang et al., 2022).
• Temporal Encoding: LIF-based phase encoders yield invertible amplitude-to-spike-time mappings, supporting direct decoding or learning-based processing in event-driven digital platforms (Lopez-Randulfe et al., 2023).

The selection or adaptation of event policy is thus guided by the anticipated signal structure and downstream processing constraints.

7. Comparison with Uniform-Rate ADCs and Broader Implications

Event-driven architectures fundamentally reallocate power and bandwidth budget toward information-rich periods, minimizing redundancy present in uniform sampling. Unlike traditional ADCs, all event-driven schemes eliminate uninformative conversions, making them particularly advantageous for sparse, bursty, or highly dynamic signals. The incorporation of address-event buses and spike-based protocols facilitates seamless interfacing with SNNs and neuromorphic hardware, increasingly critical for edge-intelligent and always-on applications (Narayanan et al., 2023, Lopez-Randulfe et al., 2023). The modularity and scalability of these architectures are further evidenced by their adaptability to multi-channel acquisition, frequency-agnostic operation, and robust performance across a diversity of analog input domains.

The field continues to integrate new algorithmic advances (e.g., FRI recovery, modulo-EDS), improved silicon implementations, and cross-disciplinary interfaces, pointing to ongoing reductions in power floor, area, and system latency while supporting direct digital and neuromorphic integration.