Event-Based Neuromorphic Computing

• Event-based neuromorphic computing is defined by asynchronous, spike-driven processing that triggers computation only upon meaningful input events.
• It pairs co-localized memory with processing to achieve ultra-low power consumption and real-time, on-chip inference, as demonstrated in object detection and gesture recognition.
• Advanced event-driven algorithms, including gradient-based backpropagation, enable efficient mapping of batch-trained networks onto energy-proportional hardware.

Event-based neuromorphic computing is a computational paradigm that merges asynchronous, spike-driven sensing with co-localized memory and computation—distinguishing itself fundamentally from clock-driven, dense-sampling architectures characteristic of contemporary digital deep learning accelerators. Computation and communication occur strictly upon the arrival of discrete “events” (typically spikes), rather than on a fixed clock, enabling ultra-low-latency, energy proportionality, and natural alignment with sparse, real-world signals. This paradigm enables real-time, edge-based inference and learning at power budgets orders of magnitude below conventional platforms, as exemplified by recent demonstrations of on-chip object detection, gradient-based learning, and event-based optimization kernels (Caccavella et al., 2023, Pehle et al., 2023, Nguyen et al., 13 Aug 2025).

1. Principles of Event-Based Neuromorphic Systems

Fundamental principles of event-based neuromorphic computing include asynchronous event-driven processing, sparse communication, and co-location of memory and computation. In contrast to rate-based or frame-based systems, event-based platforms process information only when meaningful changes are detected, such as a pixel in a dynamic vision sensor (DVS) crossing a brightness threshold, which triggers the emission of an event packet $e_i=(x_i, y_i, t_i, p_i)$ where $(x_i, y_i)$ are coordinates, $t_i$ the timestamp, and $p_i$ the polarity (Caccavella et al., 2023).

Modern neuromorphic processors, such as SynSense Speck, Intel Loihi, and SpiNNaker2, operate a mesh of local processing engines or cores that consume negligible power while idle and awaken only in response to incoming events (Caccavella et al., 2023, Gonzalez et al., 9 Jan 2024). Each processing element typically updates state and emits spikes only on event arrival, in a strictly asynchronous, no-global-clock manner. This activity-driven design exploits both local sparsity (only impacted neurons update) and temporal sparsity (computation stalls entirely when the environment is quiescent) (Gonzalez et al., 9 Jan 2024).

Memory is physically co-located with computational units, typically as small-weight SRAMs or, for analog/memristive instantiations, as nonvolatile physical devices directly in the synaptic path (Wang et al., 5 Sep 2025), which eliminates the von Neumann bottleneck associated with shuttling activations and weights between separate memory and compute resources.

2. Computational Models: Asynchronous Spiking Neurons and Event-Driven Processing

The core computational element is the spiking neuron, typically following an integrate-and-fire (IF) or leaky IF (LIF) model. In the standard IF implementation on SynSense Speck or digital cores, the membrane potential $U(t)$ is incremented discretely at each event, with firing and reset governed by membrane threshold crossings:

$$U(t) = U(t-1) + W X(t) - S_{\mathrm{out}}(t-1) \cdot \theta$$

where $W$ are synaptic weights, $X(t)$ is the spike input vector, $\theta$ the threshold, and $S_{\mathrm{out}}(t-1)$ the number of output spikes at previous step (Caccavella et al., 2023).

To bridge the sim-to-real gap between clock-driven training and event-driven, multi-precision hardware, the “multi-spike” IF model is used. In this variant, the output is:

$$S_{\mathrm{out}}(t) = \begin{cases} \left\lfloor \dfrac{U(t)}{\theta} \right\rfloor & \text{if } U(t) > \theta, \ 0 & \text{otherwise.} \end{cases}$$

This captures the possibility of a burst of spikes per step, and is essential when mapping batch-trained networks onto per-event hardware (Caccavella et al., 2023).

Network architectures are constructed by wiring such neurons into convolutional, feedforward, or recurrent topologies, where propagation occurs only on events (convolutions, pooling, fully connected, or recurrent). Hardware instantiations, such as Speck and Loihi, provide tightly coupled local weight RAMs and state stores per neuron or per core, and exploit event multicast and routing to deliver strictly local, parallel updates (Caccavella et al., 2023, Gonzalez et al., 9 Jan 2024, Nguyen et al., 13 Aug 2025).

3. Training, Inference, and Event-Based Learning Rules

To enable gradient-based learning on event-driven hardware, event-based backpropagation algorithms have been developed. EventProp is one instance that computes exact gradients by treating spike times as differentiable events, rather than relying on dense voltage sampling or rate codes (Pehle et al., 2023, Béna et al., 19 Dec 2024).

Given a parameterized network generating spike trains $\{t_i^n\}$, the loss $L(\theta)$ may depend on both spike times and voltages; its derivative w.r.t. $\theta$ can be expressed in terms of adjoint variables evaluated at event times. The event-based estimator for the gradient is: $$\hat{G}(\theta) = \sum_{n,i} \alpha_{n,i}(t_i^n; \theta) \cdot \frac{\partial t_i^n}{\partial \theta}$$ where $\alpha_{n,i}$ are adjoint weights accumulated only at spikes (Pehle et al., 2023).

This algorithm substantially reduces memory and communication requirements: only spike times and optionally a few voltage samples are needed, yielding 10×–20× efficiency gains in bandwidth and energy over surrogate-gradient methods that require dense, clock-driven sampling (Pehle et al., 2023, Béna et al., 19 Dec 2024). Recent demonstrations on SpiNNaker2 show batch-parallelized, on-chip training of multi-layer SNNs using event-driven gradient routing, achieving $30\times$ improvements in energy per training step compared to GPU references, with sparsity preserved in both forward and backward passes (Béna et al., 19 Dec 2024).

To maintain system stability and respect hardware limits, additional regularization is applied. For inference, a firing rate penalty is included in the composite loss: $$L = L_{\mathrm{det}} + \lambda \sum_{t=1}^{T} \sum_{l=1}^{L} \sum_{i=1}^{N_l} F_{l,i}[t]$$ enabling Pareto-driven tradeoff between precision and average power consumption (Caccavella et al., 2023).

4. Event-Driven Pipelines and Hardware Implementations

Modern event-based neuromorphic pipelines integrate dynamic vision sensors (DVS) or other event sources at the front end, specialized event routing protocols (such as Address-Event Representation, AER), and asynchronous spike-based processing back ends (Caccavella et al., 2023, Wang et al., 5 Sep 2025, Nguyen et al., 13 Aug 2025).

Key features of state-of-the-art systems include:

• Event-driven sensors (e.g., 128x128 DVS) output sparse event streams $e_i$.
• Asynchronous processors (e.g., SynSense Speck, Intel Loihi 2, SpiNNaker2) implement event-driven convolutions, multi-core SNNs, or analog neuron arrays, with on-chip memory (8–16 bit precision) and tight memory-bandwidth budgets (Caccavella et al., 2023, Gonzalez et al., 9 Jan 2024, Nguyen et al., 13 Aug 2025, Wang et al., 5 Sep 2025).
• Event routing via hardware multicasting (NoCs, routers, or differential analog lines) delivers spikes without central arbitration (Gonzalez et al., 9 Jan 2024).
• Direct hardware mapping of network topologies (convolutional, fully connected, event-centric recurrent) onto many-core or mixed-signal substrates (Gonzalez et al., 9 Jan 2024, Wang et al., 5 Sep 2025, Abdollahi et al., 10 Oct 2024).

Power consumption in such systems is tightly coupled to event rate, as the power has leading-order dependence on the number of synaptic operations per second: $$P \approx P_{\mathrm{idle}} + \alpha(\mathrm{SynOps/s})$$ Empirically, face detection networks on Speck achieved mAP[0.5]=0.622 at 19.4 mW for moderate regularization, with high-throughput event pipelines supporting 3.2%%%%15$L(\theta)$16%%%% spikes/s (Caccavella et al., 2023). Mixed-signal and memristive SNNs demonstrated >100 TSOPS/W efficiency on DVS128 Gesture, with latencies in the tens of microseconds regime (Wang et al., 5 Sep 2025).

5. Event-Centric Algorithmic Innovations and Application Domains

Event-based neuromorphic computing has led to distinctive algorithmic patterns:

• Event-driven optimization: Classical robust model fitting tasks (e.g. RANSAC) have been recast as spiking programs, in which every phase—random sub-sampling, model update, consensus counting—is triggered by explicit spike-timed events. Key algorithmic constructs include outer-product lifting of gradient updates via Kronecker (spiking) coding, matrix multiply emulation with convolutional synapses, and PRG thresholding for sampling decisions (Nguyen et al., 13 Aug 2025).
• Backpropagation and learning: Surrogate-gradient and event-propagation algorithms enable in-hardware exact or approximate gradient computation with state-of-the-art accuracy (Caccavella et al., 2023, Béna et al., 19 Dec 2024, Pehle et al., 2023).
• Quantization and calibration: Weight quantization (to 8 bits), input event histogramming, and layer normalization bridge the clock-to-event training gap, enabling direct deployment of batch-trained SNNs onto resource-constrained event-driven hardware (Caccavella et al., 2023).
• Hybrid architectures: Systems such as MENAGE employ analog-digital mixed-signal circuits with time-multiplexed “virtual neurons,” using event-memory buffers and ILP-guided resource assignment to balance model size, utilization, and power (Abdollahi et al., 10 Oct 2024).
• Application domains: Demonstrated use cases include event-driven object detection, robust geometric estimation, large-scale sequence modeling, and continuous learning at the edge, spanning mobile robotics, vision, edge AI, and sensor fusion (Caccavella et al., 2023, Nguyen et al., 13 Aug 2025, Gonzalez et al., 9 Jan 2024, Wang et al., 5 Sep 2025).

6. Performance, Energy Scaling, and Tradeoffs

A defining property of event-based neuromorphic systems is energy-proportional computation: all dynamic energy and bandwidth are tightly linked to the volume of actual measured events, not dataset or network size. This is in contrast to synchronous accelerators, which update every neuron and synapse at every clock tick, regardless of input activity.

The following tradeoffs characterize system-level behavior:

Regularization $\lambda$	mAP[0.5]	Average Power (mW)	Spikes/s (10$^5$)	SynOps/s (M)
$1 \times 10^{-4}$	0.868	33	--	39
$3 \times 10^{-3}$	0.622	19.4	3.2	4.6
$5 \times 10^{-3}$	0.565	11.8	--	--

Increasing regularization reduces average spikes/s and power at the expense of detection precision (Caccavella et al., 2023). Empirical evaluations show a nearly linear relationship between synaptic activity and power; Pareto fronts empirically quantify the exact energy-accuracy regimes available to practitioners.

End-to-end event-based pipelines also demonstrated 85% energy savings relative to CPU baselines for robust fitting (Nguyen et al., 13 Aug 2025) and $>100\,\mathrm{TSOPS/W}$ for high-speed, fully-analog gesture recognition. On large benchmarks, batch-parallelized event-based learning achieved $30\times$ lower energy per step relative to GPUs for comparable accuracy (Béna et al., 19 Dec 2024).

7. Context, Significance, and Future Directions

The event-based neuromorphic paradigm as embodied by these systems evidences a fundamental shift in how high-throughput, low-power perception and learning can be implemented. By matching the sparsity and asynchrony of real-world signals, and tightly co-designing hardware with event-driven algorithms, the paradigm achieves latency and energy levels compatible with always-on edge inference, continual adaptation, and real-time sensor fusion.

Significant challenges remain, including closing the sim-to-real gap for event-based training, scaling up to large and heterogeneous networks, and exploring the boundaries of physical device variability and non-idealities in analog/memristive substrates. Rapid hardware progress and the emergence of event-based backpropagation, event-centric optimization, and quantized calibration routines, however, position event-based neuromorphic systems as a practical route toward sustainable, robust AI at scale (Caccavella et al., 2023, Pehle et al., 2023, Wang et al., 5 Sep 2025, Béna et al., 19 Dec 2024).