Event-Based Neuromorphic Computing

• Event-based neuromorphic computing is a paradigm that processes asynchronous, timestamped events to mimic biological sensing with high temporal fidelity.
• Core algorithms exploit time-surface descriptors and hierarchical spiking neural networks to extract spatial and temporal features efficiently.
• Hardware architectures integrate asynchronous sensors with digital, analog, or photonic processors to achieve scalable, energy-efficient, and low-latency computation.

Event-based neuromorphic computing is a paradigm in information processing that leverages the fine-grained spatio-temporal structure of asynchronous events, primarily inspired by biological sensing and signaling, to achieve high-performance, low-latency, and energy-efficient computation. Event-based systems integrate sensing, memory, and compute using architectures where the fundamental unit of data is a timestamped “event” (or spike), emitted only when and where change occurs in the signal. This approach contrasts with conventional frame-based or clock-driven systems that process periodic, dense, and often redundant data. By operating on a per-event basis, event-driven neuromorphic hardware and algorithms directly exploit signal sparsity, temporal fidelity, and locality for applications ranging from vision and audition to control, learning, and large-scale brain emulation.

1. Principles of Event-Driven Sensory Processing

Event-based sensors, such as Dynamic Vision Sensors (DVS) and Address Event Representation (AER) arrays, produce streams of events of the form $e = (x, y, t, p)$, where $(x, y)$ are pixel coordinates, $t$ is a microsecond-resolved timestamp, and $p$ is a polarity flag indicating an increase or decrease in signal intensity. Each pixel operates asynchronously and emits events only on local changes, rendering the data stream sparse and precisely timed (Haessig et al., 2018, Skontranis et al., 17 May 2025, Paredes-Valles et al., 25 Nov 2025). This encoding preserves temporal relationships vital in fast, dynamic environments and drastically reduces redundant information compared to frame-based sensors.

The event-driven model naturally aligns with spiking neural networks (SNNs), in which neurons emit discrete spikes based on their membrane potential dynamics. SNNs implement biologically inspired leaky integrate-and-fire (LIF) or adaptive LIF (ALIF) models, propagating spikes through hierarchies of synapses with temporal kernels. Unlike rate-based models, these networks operate on the native timescale of events, enabling direct realization of algorithms such as event-driven convolution, recurrent integration, or local plasticity (Caccavella et al., 2023, Renner et al., 2019).

2. Core Algorithms and Representational Hierarchies

A fundamental methodological advance is the construction of hierarchical, time-oriented representations from event streams. An example is the “time-surface” descriptor $$S_i(u, v) = \exp\left(-\frac{t_i - t_{u,v}}{\tau}\right)$$, which encodes the recent history of activity in a local spatio-temporal neighborhood around each event. This approach transforms unordered event streams into compact, feature-rich mappings sensitive to both spatial and precise temporal context (Haessig et al., 2018).

Event-based systems exploit unsupervised hierarchical architectures, such as sparse-coded multi-layer networks, that project time-surfaces onto learned dictionaries of basis functions and encode similarity via output spike delays. Layer-wise transforms with increasing spatial and temporal receptive fields extract increasingly abstract and invariant features, culminating in robust recognition pipelines that can be implemented in online or offline event-driven fashion (Haessig et al., 2018). Hardware-friendly pipelines may employ convolutional SNNs, dynamic synaptic weights, and binarized or quantized activations to further leverage event sparsity and achieve computational scalability.

Other algorithms, such as event-based region-of-interest (ROI) prediction (e.g., the TRIP framework on SENECA), use cascaded event-driven CNNs to predict dynamic attentional windows. Differentiable cropping via trainable kernels and integer arithmetic pooling allows for highly-efficient, region-adaptive processing pipelines tailored for high-resolution event streams (Arjmand et al., 2024).

3. Hardware Architectures and System Integration

Event-driven neuromorphic systems typically couple asynchronous sensors with specialized processor arrays designed for sparse, parallel spike-based computation. Digital platforms (e.g., Intel Loihi, SpiNNaker2, SynSense Speck, HiAER-Spike) use mesh or hierarchical networks-on-chip for low-latency multicast spike routing, on-chip SRAM/DRAM or HBM for sparse data structures, and massive parallelism across neuron cores (Gonzalez et al., 2024, Béna et al., 2024, Frank et al., 20 Feb 2026).

Analog and mixed-signal systems (e.g., MENAGE, integrated memristive SNNs) extend efficiency by incorporating C2C-ladder or memristor crossbars as synapses and compact RC or op-amp based neuron circuits with features such as proportional time scaling and virtual neuron multiplexing to reduce area and power (Abdollahi et al., 2024, Wang et al., 5 Sep 2025). Photonic event-driven processors, such as VCSEL-based time-delayed reservoirs, leverage ultrafast time constants and all-optical spiking for sub-microsecond inference and inherent scalability (Skontranis et al., 17 May 2025).

Common across platforms is a memory architecture that exploits the sparse, locally indexed nature of event and synaptic traffic. Adjacency lists or compressed sparse row formats and pointer-based event routing minimize memory transactions per event; two-phase pipelines (active event look-up then synaptic update) ensure each computation is proportional to actual activity (Frank et al., 20 Feb 2026).

4. Event-Based Learning: Offline, Online, and Local Rules

Event-driven learning encompasses both offline (batch) and online (local, event-driven) training algorithms, with an increasing focus on retaining temporal sparsity in both the forward and backward passes. Exact event-based backpropagation (EventProp) propagates error signals only at spike times, computing gradients via adjoint ODEs or optimized discrete-time dynamics (Béna et al., 2024, Pehle et al., 2023). This spike-based approach dramatically reduces information requirements compared to surrogate-gradient (voltage-sampling) methods and enables scalable, energy-efficient learning in both digital and mixed-signal hardware.

Local plasticity rules, such as Event-based Three-factor Local Plasticity (ETLP), integrate presynaptic spike traces, postsynaptic membrane voltages, and projected teaching signals for fully local, efficient weight updates that can be mapped as simple hardware primitives (LUTs, accumulators) (Quintana et al., 2023). Such rules are shown to provide competitive accuracy with orders-of-magnitude savings in computation and memory per event.

Hardware-friendly learning approaches also include spike-based STDP, hardware-aware quantization and event-driven batch-parallelized BPTT, all mapped efficiently to neuromorphic backing via asynchronous event packet routing and local storage (Béna et al., 2024, Shoesmith et al., 6 Mar 2025).

5. Application Domains

Event-based neuromorphic computing is demonstrated in a range of spatio-temporal tasks:

• Neuromorphic vision (e.g., DVS letter/digit/suit recognition, event-based gesture, face, and pupil detection): Hierarchical sparse-coded and convolutional SNNs achieve near-perfect accuracy with sub-millisecond latency on low-power embedded hardware, often with 40×–100× reductions in computation and energy over frame-based methods (Haessig et al., 2018, Caccavella et al., 2023, Paredes-Valles et al., 25 Nov 2025, Arjmand et al., 2024).
• Attention and tracking: Dynamic neural field attractors and event-driven winner-take-all architectures on neuromorphic chips maintain robust tracking of attended targets under distractors or motion pauses (Renner et al., 2019).
• Control and robotics: On-chip event-driven SNN controllers achieve <0.3 ms latencies in UAVs and real-time adaptation to unknown disturbances through local reinforcement learning, supporting fast closed-loop control architectures orders-of-magnitude faster and more energy-efficient than CPU+frame vision approaches (Vitale et al., 2021).
• Audio and speech: Event-wise deep state-space models and SNNs process millions of asynchronous cochlear or microphone events, achieving state-of-the-art or super-human performance in tasks such as keyword spotting and speech command recognition at millisecond latencies (Schöne et al., 2024, Shoesmith et al., 6 Mar 2025).
• Power system monitoring: Time-series from grid sensors (PMU) are encoded to sparse spike trains, processed in SNNs via QR-based subspace selection and STDP or supervised ANN→SNN conversion, reducing energy by >80% with comparable accuracy to conventional ML (Mahapatra et al., 2020).

In tabular form, a subset of hardware platforms and application benchmarks:

System	Application	Neurons	Energy (μJ)	Latency (μs)	Accuracy (%)
HiAER-Spike	DVS Gesture	17,709	510.7	1,156.2	68.75
Menage (CMOS)	CIFAR10-DVS	–	–	–	12.1 TOPS/W
Memristive SNN	DVS Gesture	–	–	–	93.06
Speck2f	Pupil Tracking	–	<12 mW/eye	100 Hz	–
VCSEL-Res	Flow Cytometry	200 vnodes	<2 mW	<2,000 ns	95.8
SpiNNaker2	Speech	9,907	459,000	–	94.13

6. Scalability, Performance, and Hardware-Algorithm Co-Design

Modern event-based neuromorphic systems are engineered for scalability along both neuron/synapse count and event throughput. Examples such as HiAER-Spike demonstrate platforms with up to 160 million neurons and 40 billion synapses, operating faster than real time via hierarchical address-event routing, pointer-based sparse connectivity, and distributed simulation (Frank et al., 20 Feb 2026). Unified Python APIs and hardware abstraction layers shield users from low-level mapping details, enabling transparent scaling from desktop simulation to cluster-sized hardware deployment.

Energy efficiency and latency are tightly coupled to the event-driven model: only active elements consume dynamic power, with per-event processing costs as low as a few nJ, and update intervals in the microsecond regime. Mixed-signal and photonic approaches, using virtual neurons, analog RC integration, and optical delay reservoirs, further improve power density and reduce inference times to the nanosecond domain, at modest trade-offs in maximum model size or weight programming precision (Abdollahi et al., 2024, Wang et al., 5 Sep 2025, Skontranis et al., 17 May 2025).

A unifying theme is hardware-algorithm co-design: network architectures, learning rules, and sparsity constraints are tailored to fit architectural primitives (e.g., on-chip BRAM, per-event accelerators, low-precision arithmetic) and vice versa, with iterative benchmarking on canonical tasks (e.g., DVS-Gesture, MNIST, CIFAR10-DVS, SHD).

7. Challenges, Open Problems, and Future Trajectories

Despite substantial advances, event-based neuromorphic computing faces several active research areas:

• Online learning and local plasticity: Realizing robust, online, hardware-friendly learning compatible with large-scale SNNs, especially in analog/mixed-signal and memristive platforms, is an ongoing effort (Pehle et al., 2023, Quintana et al., 2023). EventProp and three-factor rules provide promising directions but require further scaling, architectural embedding, and resilience to device variation.
• Asynchronous deep models: Pushing deep, purely event-driven recurrent or state-space models (e.g., Event-SSM) into hardware for long-event-sequence processing remains in early stages, particularly for analog or mixed-signal implementations (Schöne et al., 2024).
• Co-design of sensor-processor pipelines: Tighter integration of sparse, edge-resident event sensors with in-sensor or near-sensor neuromorphic processing (e.g., for ROI cropping) can further reduce data bandwidth, latency, and power (Arjmand et al., 2024).
• Event-based simulation and device modeling: Efficient and accurate event-driven simulation of stochastic nanoscale components (memristors) with combined long-term and volatile dynamics is essential for predictive modeling and future hardware design (El-Geresy et al., 2024).
• Standardization, benchmarking, and software tooling: Cross-platform APIs, hardware simulators, and open, large-scale benchmarks are needed for broader accessibility and reproducibility.

In conclusion, event-based neuromorphic computing provides a rigorous foundation and practical toolkit for sparse, fast, and energy-efficient intelligent signal processing. It has moved from single-chip demonstrations to cluster-scale, real-world deployment across vision, audio, control, edge AI, and beyond, with continuing advances in algorithms, hardware design, and neural modeling (Haessig et al., 2018, Frank et al., 20 Feb 2026, Béna et al., 2024, Arjmand et al., 2024, Abdollahi et al., 2024).