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Asynchronous Delta Modulation (ADM)

Updated 23 March 2026
  • ADM is an event-driven analog-to-digital conversion technique that encodes changes as UP/DN events based on a configurable threshold, reducing redundant data transmission.
  • ADM employs adaptive thresholding to dynamically adjust the quantization step size, balancing high-fidelity response during rapid signal changes with noise suppression during low activity.
  • ADM architectures, including hybrid CMOS-memristor designs, enable energy-efficient, always-on operation in biomedical sensors, neuromorphic systems, and spike-based IoT front-ends.

Asynchronous Delta Modulation (ADM) is an event-driven analog-to-digital conversion technique that encodes temporal signal variation as sparse streams of discrete “UP” or “DN” events. Unlike synchronous delta modulation, which samples at uniform intervals and outputs quantization steps at every clock tick regardless of input motion, ADM operates continuously and generates events only when the instantaneous quantization error exceeds a configurable threshold. This data-driven nature enables ADM to achieve significant reductions in event rate and power consumption, making it well-suited for always-on biomedical sensors, neuromorphic systems, and spike-based IoT front-ends (Sharifshazileh et al., 2022, Guo et al., 5 Dec 2025).

1. Fundamental Principles of Asynchronous Delta Modulation

ADM encodes only the changes in the input waveform, x(t)x(t), forming an output event train whose rate closely tracks signal dynamics. The ADM quantizer maintains a running estimate x^[n1]\hat{x}[n-1] and, at each computational step, evaluates the error:

e[n]=x[n]x^[n1].e[n] = x[n] - \hat{x}[n-1].

An “UP” event is triggered if e[n]+Δe[n] \geq +\Delta, and a “DN” event if e[n]Δe[n] \leq -\Delta. Upon an event, the reconstructed value is updated (x^[n]=x^[n1]±Δ\hat{x}[n] = \hat{x}[n-1] \pm \Delta), and the integrator resets. Non-crossing of thresholds yields no output, resulting in event sparsity. The spike rate for a sinusoidal input of amplitude AA and frequency ff is approximately

RsAfTrfrΔ,R_s \propto \frac{A f}{T_{\mathrm{rfr}} \Delta},

where TrfrT_{\mathrm{rfr}} is the refractory period and Δ\Delta is the comparator threshold (Sharifshazileh et al., 2022).

2. Adaptive Thresholding and Step-Size Control

ADM systems often incorporate adaptive thresholding mechanisms to automatically tune the step size, Δ\Delta, in response to input signal statistics. A general first-order adaptive rule is:

$\Delta[n+1] = \Delta[n] + \alpha\,\mathrm{sgn}(e[n]) - \beta\,\Delta[n},$

where α\alpha and β\beta are positive constants. This approach increases the threshold to sparsify output during intervals of sustained small errors and decreases it to preserve fidelity during low activity (Sharifshazileh et al., 2022).

Implementations vary:

  • In (Sharifshazileh et al., 2022), envelope detection followed by dual low-pass filtering (distinct time constants) and a current-mode WTA circuit enable the system to raise Δ\Delta for low-salience background, while freezing the threshold during transients, retaining encoding resolution for high-precision events.
  • In hybrid CMOS-memristor encoders, as in (Guo et al., 5 Dec 2025), the ADM threshold Δ(t)\Delta(t) is dynamically set by the memristor’s volatile conductance state (Δ(t)=GTIAIm(t)\Delta(t) = G_{\mathrm{TIA}} I_m(t), with Im=Vread/RmemI_m = V_{\mathrm{read}}/R_{\mathrm{mem}}), providing biologically inspired adaptation without static control energy.

3. Encoder Architectures and Event-Based Operation

An ADM front-end typically comprises:

  • Signal conditioning (e.g., LNA, OTA with capacitive feedback)
  • Comparators evaluating VintegV_{\mathrm{integ}} against symmetric thresholds (Vref±ΔV_{\mathrm{ref}}\pm\Delta)
  • Event encoder logic that generates UP/DN digital pulses and Ack signals for integrator reset
  • Refractory/hold circuit preventing spurious events within a dead-time TrfrT_{\mathrm{rfr}}
  • Adaptive thresholding circuitry (envelope detector, low-pass filters, WTA comparator)
  • In hybrid designs, a transimpedance amplifier derives Δ\Delta from memristor current, with off-chip or integrated spike-triggered programming to modulate device conductivity (Guo et al., 5 Dec 2025, Sharifshazileh et al., 2022).

During operation, the ADM remains quiescent during periods of small input variation and emits temporally precise events on significant signal excursions. Adaptive threshold blocks may inhibit threshold updates on rapid excursions, maintaining high encoding precision during clinically or computationally salient events (e.g., seizure HFOs).

4. Theoretical Properties and Error Analysis

Modified ADM algorithms provide guarantees on signal tracking error under specific bounded-variation assumptions. For an encoding scheme where a single bit hk{±1}h_k\in\{\pm1\} is transmitted per sample and step-size adaptation obeys a three-state rule (ramp-up, hold, decrease), the quantizer error can be bounded by O(aM+D)O(aM+D), where aa is the growth factor for MkM_k, MM the minimum allowed step size, and DD the local signal variation bound (Dokuchaev, 2013). This ensures recovery from input discontinuities and suppression of steady-state error, subject to appropriate parameter tuning.

5. Performance Metrics and Comparative Evaluation

ADM performance is characterized by root-mean-square error (RMSE) versus Δ\Delta and TrfrT_{\mathrm{rfr}}, total event rate, power, and area efficiency. Experimental findings include:

  • Background segments (“noise-only”) yield near-zero spike rates with adaptive Δ\Delta, while salient events are densely encoded, supporting event reduction exceeding 80%80\% relative to fixed-threshold baselines (Sharifshazileh et al., 2022).
  • A 180 nm CMOS prototype ADM consumes approximately 25μW2–5\,\mu\mathrm{W} (plus 1μW1\,\mu\mathrm{W} for the adaptive-Δ\Delta block) and occupies 0.03mm2\sim0.03\,\mathrm{mm}^2 (Sharifshazileh et al., 2022).
  • In hybrid CMOS-memristor systems, adaptive ADM encoders matched to a fixed spike budget achieve higher Pearson correlation coefficients with speech RMS envelopes, particularly during onset-dominated segments (radaptive=0.677r_{\mathrm{adaptive}}=0.677 vs rfixed0r_{\mathrm{fixed}}\approx 0) and better preserve fine temporal structure in multi-channel cochleagrams (Guo et al., 5 Dec 2025).

6. Design Trade-offs and Application Domains

Critical trade-offs in ADM design include the balance between adaptation speed and event sparsity. Fast adaptation can suppress undesired baseline spikes but may attenuate legitimate signal features; slow adaptation enhances fidelity but risks elevated event rates in dynamic backgrounds. Time-constant and gain parameters, as well as device-level variability (e.g., memristor decay τ1,2\tau_{1,2}), must be carefully calibrated for application requirements (Sharifshazileh et al., 2022, Guo et al., 5 Dec 2025).

ADM’s principal applications are in always-on ECG/EEG/EMG monitoring, neuromorphic health tracking, minimally invasive IoT sensors, auditory encoding with temporal precision constraints, and, more generally, in event-driven interfaces for edge neural networks. The circuit compactness and low power profile are particularly advantageous where classical ADC modalities are infeasible (Sharifshazileh et al., 2022, Guo et al., 5 Dec 2025).

7. Advanced Implementations and Future Directions

Emergent ADM architectures integrate adaptive threshold modulation via inherently volatile nano-devices. The hybrid CMOS-HfTiOx_x memristor ADM encoder leverages passive relaxation and pulse-driven programming for ultra-low power, self-contained adaptation without the need for explicit RESET commands or continuous digital oversight (Guo et al., 5 Dec 2025). Monolithic co-integration is anticipated to reduce system overhead and enhance per-spike energy efficiency.

Future progress will likely extend ADM’s adaptive principles to multi-modal, multi-channel, and multi-timescale sensors, generalizing beyond audio and bio-signal front-ends into domains such as tactile sensing and event-based vision. Deep submicron CMOS, on-chip digital logic for real-time spike budgeting, and further miniaturization hold promise for embedded spike-driven signal processing architectures.

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