Mixed-Signal Analogue Front End (AFE)

• Mixed-signal analogue front ends are integrated systems that condition analog sensor signals using amplification, filtering, and programmable encoding.
• They employ low-noise amplifiers, programmable filters, and event-based modulators to achieve high dynamic range, bandwidth tuning, and energy efficiency across diverse applications.
• Design trade-offs in mixed-signal AFEs include balancing power, noise, and linearity while integrating digital calibration and control for enhanced performance.

A mixed-signal analogue front end (AFE) is a system-level electronic interface that receives analog signals from sensors or physical environments, performs amplification, frequency selection, noise filtering, and signal conditioning, and provides outputs suitable either for digital conversion or direct event-based, asynchronous communication with back-end processing engines. In the context of advanced applications—including neuromorphic processors, scientific detection instrumentation, implantable biomedical interfaces, and sensor signal conditioning—the mixed-signal AFE must balance low-noise analog design, programmable functionality, high dynamic range, bandwidth, power consumption, and robust mixed-signal integration. Recent research encompasses highly integrated event-based encoders, adaptive gain architectures for high-capacitance sensors, programmable filter banks for audio feature extraction, and advanced servo or offset cancellation for biopotential acquisition.

1. Fundamental Building Blocks of Mixed-Signal AFEs

A typical mixed-signal AFE consists of the following core components, adapted for specific application domains:

• Pre-amplifier or Low-Noise Amplifier (LNA): Converts low-amplitude sensor signals to a level suitable for further processing. For example, the SPAIC architecture employs a capacitive-feedback OTA with a DC-servo loop to establish a defined low-frequency cutoff and a tunable gain of 0–24 dB (Narayanan et al., 2023). For high-capacitance particle detectors, regulated common-gate (RCG) input stages with programmable gain provide low input impedance and precise impedance matching (Cheng et al., 2019).
• Programmable Filter or Shaping Network: Band-pass or low-pass filters employ designs such as flipped-voltage-follower (FVF) BPFs, Gm–C filter cells, cascaded RC or CR–RC shapers, or digital parametric IIR filters for frequency selection and noise suppression. The tunable 4th-order FVF BPF in SPAIC enables programmable center frequency (100 Hz–100 kHz) and Q factor control using an 8-bit CDAC (Narayanan et al., 2023).
• Programmable-Gain Amplifiers (PGA): Provide additional staged gain control. Reuse of core OTAs for LNA and PGA is common for area/power efficiency.
• Signal Modulation/Encoding: Outputs may be digitized with ADCs (SAR, Wilkinson, SAR+split-cap), time-encoded with TDCs, or converted to event-based signals via asynchronous delta modulation (ADM), pulse-frequency modulation (PFM), or integrate-and-fire neurons for neuromorphic systems (Narayanan et al., 2023).
• Mixed-Signal Digital Control and Calibration: SPI/I²C interfaces manage bias settings, programmable thresholds, filter tuning codes, and adaptation/control logic. On-chip digital controllers orchestrate calibration, temperature/offset compensation, and data flow to the digital backend.

2. Encoding Methodologies: Dual-Mode, Time-Based, and Frequency-Based

Mixed-signal AFEs employ diverse encoding techniques to bridge analog and digital domains, optimized for application context:

• Asynchronous Delta Modulation (ADM): Implements a level-crossing ADC where UP/DOWN events are generated when an input voltage crosses programmable thresholds; ensures faithful waveform reconstruction at low event rates (Narayanan et al., 2023). Event generation is defined by:

$$\text{Emit UP when } v(t) \geq V_{\mathrm{th,up}}, \quad \text{Emit DOWN when } v(t) \leq V_{\mathrm{th,dn}}$$

Piecewise-constant reconstruction follows:

$\hat v(t) = v(t_0) + \sum_{k\,:\,t_k<t} \Delta_k$

• Pulse-Frequency Modulation (PFM) with LIF Neurons: Conditioned analog current is injected into a leaky-integrate-and-fire neuron, generating spikes at a rate proportional to input DC level:

$$C_m \frac{dV_m}{dt} + g_L (V_m - V_{\mathrm{rest}}) = I_{\mathrm{in}}(t)$$

• Analog and Mixed-Signal ADCs and TDCs: CR–RC, RC⁴, or quasi-Gaussian shaper outputs are sampled by high linearity, low-noise ADCs (e.g., SAR, 10–12 bit) for precise amplitude readout, with auxiliary TDC logic providing arrival-time resolution in the 40–350 ps regime (Liu et al., 2015, Zhang et al., 2017). Dual-branch architectures parallelize high-speed timing and accurate energy/charge readout (Cheng et al., 2019).
• Event-Based Bus Protocols: Address-Event Representation (AER) schemes encode both spatial (channel identity) and temporal event data with handshaking, allowing asynchronous, clock-free transfer to neuromorphic computing back ends (Narayanan et al., 2023).

3. Programmability, Dynamic Range, and Frequency Tuning

Programmability in modern AFEs is critical for adapting to multiple sensors, environments, and dynamic signal conditions:

• Frequency Bandwidth Tuning: Continuous or discrete programming of filter elements (e.g., 8-bit CDACs for FVF BPFs, Gm–C banks for band-pass/low-pass) yields octave-spaced or custom filter banks spanning several decades in frequency (e.g., 100 Hz–100 kHz as in SPAIC) (Narayanan et al., 2023).
• Dynamic Range Maximization: Parallel gain paths (dual-gain, e.g., ALFE2 with HG/LG branches), gain-switching feedback architectures, and saturating filter/ADC designs enable dynamic range >40 dB for analog domains (SPAIC, 55 dB LNA; ALFE2, 16-bit total) (Narayanan et al., 2023, Matakias et al., 14 Feb 2024).
• Programmable Thresholds and Biases: On-chip DACs allow run-time threshold and bias adjustments for comparators, discriminators, and charge sensitivity, enabling per-channel or global tuning (Cheng et al., 2019, Liu et al., 2015).

4. Low-Power and Integrated Circuit Techniques

Power and area efficiency, particularly for edge and implantable use cases, necessitate advanced circuit techniques:

• Current Reuse and OTA Core Sharing: Reusing high-gm OTA cores across multiple gain or filter blocks (as in SPAIC) minimizes static power and silicon area (Narayanan et al., 2023). Stack inverters/cascoded architectures in FVF filters leverage current reuse to reduce total consumption.
• Subthreshold Operation and Bias Minimization: Event-based encoding and LIF neurons are optimized for sparse signal activity, drawing <100 nW/channel in some SPAIC configurations (Narayanan et al., 2023). OTA core currents (e.g., <40 µA per block) directly set analog noise and dynamic range bounds.
• Pseudo-Resistor and Body-Bias Techniques: Employing subthreshold MOS for high-value feedback resistors (pseudo-resistors) or digitally controlled bulk bias (as in neural AFEs) enables ultra-low-frequency pole formation without the area cost of large passive resistors (Antoniadis et al., 16 Nov 2025).
• Mixed-Signal Digital Integration: Tight coupling of digital controllers, on-chip calibration engines, and event-based communication logic allows for complex signal conditioning and control with minimal impact on analog noise (Narayanan et al., 2023).

5. Performance Metrics, Limitations, and Application Domains

Measured performance is typically validated via silicon characterization:

Metric	SPAIC (Narayanan et al., 2023)	Particle FE (Cheng et al., 2019)	PMT Readout (Liu et al., 2015)
Power/channel	<800 nW (@100 kHz)	<9 mW	n/a (~mW scale)
Input noise	1.4 µV_rms (1 Hz–1 kHz)	3.5 ke^- rms (100 pF)	0.76–0.84 mV RMS
Dynamic range	>40 dB output (SNDR)	400 fC (max)	1–4000 P.E.
Bandwidth	100 Hz–100 kHz	2.7 MHz (fast)	~30 MHz 3 dB band
Area/channel	0.09 mm^2	n/a	n/a

Limitations may include:

• Flicker and Thermal Noise: OTA-based AFEs are flicker-noise limited at low frequencies (Narayanan et al., 2023), which constrains SNR in bio-signals and ultra-low amplitude regimes.
• Comparator/Discriminator Hysteresis: Event generation accuracy is fundamentally limited by threshold dispersion and comparator noise floor (SPAIC, 3σ ≈ 900 µV) (Narayanan et al., 2023).
• Trade-Offs: Gain and signal bandwidth must be balanced against power and linearity. Aggressive power minimization may inhibit maximum available SNR or settling speed (Liu et al., 2015).

Application domains span:

• Edge neuromorphic processing with address-event interfaces and dual-mode encoding (SPAIC) (Narayanan et al., 2023).
• Particle/gas/PMT detector readout with high dynamic range and fast TDC/ADC capture (Cheng et al., 2019, Liu et al., 2015).
• Audio and speech front ends with jointly optimized filters/co-designed classifiers (Hu et al., 1 Jul 2025).
• Biomedical recording with sub-mHz offset cancellation and integrated digital calibration loops (Antoniadis et al., 16 Nov 2025).

6. Integration with Digital and Event-Based Systems

Modern mixed-signal AFEs are explicitly designed for seamless coupling with digital back ends, event-driven processors, or algorithmically optimized downstream classifiers:

• Asynchronous Event Buses: Use of Address-Event Representation (AER) enables clock-free interface to neuromorphic SNN processors (e.g., Dynap, Loihi), maintaining low system power and sparse representation (Narayanan et al., 2023).
• Digital Control and Calibration: SPI, I²C, or custom serial control interfaces orchestrate analog biasing, filter selection, gain-stage switching, and encoding mode selection, often at the per-channel level.
• Data Flow for Classification and Feature Extraction: In co-design architectures (e.g., LearnAFE), filter transfer function parameters are jointly trained with classifier weights in a hardware-in-the-loop fashion, shrinking area and power while optimizing task accuracy (Hu et al., 1 Jul 2025).

7. Design Trade-Offs and Future Directions

Dominant themes in ongoing research include:

• Power/Performance Scaling: Sub-µW/channel operation is standard for edge and implantable systems, requiring continuous innovation in biasing, current reuse, and event encoding (Narayanan et al., 2023, Antoniadis et al., 16 Nov 2025).
• Programmability and Generalization: Emphasis on general-purpose AFEs that can be digitally programmed for frequency, gain, and encoding modality broadens system applicability.
• Integration with Learning/Co-Design: Joint circuit-algorithm co-design shifts part of the optimization to the system level, allowing analog circuit parameters to be trained in-situ for specific tasks (Hu et al., 1 Jul 2025).
• Advanced Calibration and Offset Cancellation: Digital fixed-point filtering and digitally assisted biasing enable tight control of sub-mV offsets in biomedical and low-frequency domains (Antoniadis et al., 16 Nov 2025).
• Scalable Event-Driven Architectures: Emphasis on modular channel scalability (e.g., 16–64 channels per ASIC) with synchronous or sparse asynchronous outputs enables compatibility with large-scale sensor arrays and distributed neuromorphic architectures.

In summary, mixed-signal analogue front ends represent a convergence point for advanced analog design, digital control, and system-level co-optimization, enabling ultra-low-power, high-dynamic-range, event-based encoding compatible with next-generation edge, scientific, and biomedical applications (Narayanan et al., 2023, Cheng et al., 2019, Liu et al., 2015, Hu et al., 1 Jul 2025, Antoniadis et al., 16 Nov 2025).