Photonic In-Memory Computing

• Photonic in-memory computing is a paradigm that integrates optical memory elements with analog optical signal processing to bridge the gap between storage and computation.
• Key architectures, including PCM cells, memristor-integrated resonators, and photonic SRAM, enable high-speed and energy-efficient matrix–vector and tensor operations.
• System-level integration with dense WDM schemes and hybrid photonic-electronic approaches delivers scalable performance for AI, scientific computing, and neuromorphic applications.

Photonic in-memory computing is the class of computational architectures in which photonic non-volatile or volatile memory elements are integrated natively into the dataflow of analog optical signal processing, thereby collapsing the conventional separation of memory and arithmetic found in digital von Neumann systems. These architectures exploit light–matter interaction phenomena—phase-change, charge-trapping, plasma dispersion—inside silicon or compound-photonic platforms, enabling data storage, multiplication, and accumulation to occur at the speed and bandwidth of light. By aligning storage and compute, photonic in-memory approaches target orders-of-magnitude improvements in throughput, latency, and energy efficiency for matrix–vector and tensor operations fundamental to machine learning, scientific computation, and communications.

1. Device Architectures: Materials, Structures, and Non-Volatility

Photonic in-memory elements fall chiefly into PCM-based cells, memristor-integrated microring resonators, programmable optical latch circuits, and photonic SRAM arrays.

• Phase-Change Material (PCM) Devices: Devices based on Ge₂Sb₂Te₅ (GST), Ge₂Sb₂Se₄Te₁, Sb₂Se₃, or Sb₂S₃ enable non-volatile weight storage via optical state-dependent absorption or refractive index modulation. In waveguide cross-sections, a thin PCM layer modulates transmission according to its crystallization state, directly encoding a scalar weight into the cell’s transmittance $T$ or resonance wavelength. Typical programming energies span tens of fJ–nJ, precision up to 7 bits (14 levels), and endurance of 10³–10⁸ cycles, with retention times exceeding 10 years (Ríos et al., 2018, Kari et al., 2024, Charalampous et al., 5 Aug 2025).
• Memristor-Resonator Integration: III–V/Si hybrid platforms realize non-volatile phase shifters (“memresonators”) by integrating metal-oxide (Al₂O₃/HfO₂) memristors within silicon or compound microring or waveguide circuits (Tossoun et al., 2023, Cheung et al., 2023). These elements use resistive-switching filaments to control free-carrier density, shifting the ring resonance and thus modulating phase and amplitude with retention times up to 24 hours, sub-pJ write energies, and sub-ns switching.
• Photonic SRAM and Logic Latch Circuits: pSRAM cells employ cross-coupled silicon microring resonators and photodiodes to form bistable optical latches, supporting GHz–tens of GHz write/read rates, and energy per transition of ~0.5–1 pJ/bit (Kaiser et al., 28 Jun 2025, Arockiaraj et al., 31 Jan 2026). Enhanced designs embed Boolean logic, such as in-memory XOR (X-pSRAM), achieving 10 GHz operation and 13.2 fJ/bit XOR energy (Kaiser et al., 28 Jun 2025). Optical set–reset latches utilizing universal optical logic gates have also been shown, providing <50 fJ/bit storage with 10–20 ps switching (Ashtiani, 2024).
• Volatile/Non-Volatile Dual-Mode Memory: Recent multifunctional cells combine nonvolatile PCM weighting with ultrafast, volatile silicon PN junction tuning, enabling coarse/fine update hierarchies for mixed-precision training and inference (Kari et al., 2024, Charalampous et al., 5 Aug 2025).

2. Operating Principles and In-Memory Compute Primitives

All leading photonic in-memory architectures realize vector-scalar or vector-matrix multiplication intrinsically, with direct mapping between physical memory state and computational weight:

• Scalar-multiply primitive: The optical input’s amplitude, pulse energy, or wavelength-division channel is multiplicatively attenuated by the memory-cell’s transmission or phase, yielding $y = T \cdot x$ (attenuation) or $y = x \exp(i\Delta\phi)$ (phase mode), directly in the device (Ríos et al., 2018, Zhou et al., 2023, Wijeratne et al., 23 Mar 2025).
• Crossbar vector/matrix compute: Arrays of photonic memory cells (PCM or ring-based) implement matrix–vector products through wavelength-multiplexed busses, optical combiners, and integrated photodiodes performing analog accumulation. In WDM enhanced designs, each channel encodes a dimension of the vector, realizing parallel $y_i = \sum_j w_{ij} x_j$ updates (Ríos et al., 2018, Zhou et al., 2023, Wijeratne et al., 23 Mar 2025).
• Bitwise and logic primitives: pSRAM architectures with embedded logic gates (e.g., X-pSRAM) compute Boolean functions (XOR) between stored and input bits fully in the optical domain, supporting WDM massive parallelism for binary neural networks, cryptography, or hyperdimensional computing (Kaiser et al., 28 Jun 2025).
• Synaptic and neural primitives: Photonic SNNs integrate PCM synaptic arrays (programmable attenuation) and GST-based integrate-and-fire neurons to realize event-driven “in-memory” neuromorphic processing, leveraging WDM for input fan-in and parallelism (Chakraborty et al., 2018).

3. Performance Metrics and Comparative Analysis

Photonic in-memory computing technologies achieve performance metrics that, in key applications, significantly exceed conventional transistor-based memory-compute fabrics:

Metric	Value / Range	Platform	Source
Energy/bit (write/XOR)	0.15 pJ – 13 fJ	Memresonator/X-pSRAM	(Tossoun et al., 2023, Kaiser et al., 28 Jun 2025)
Switching speed	300 ps – 20 GHz	Memresonator/pSRAM/X-pSRAM	(Tossoun et al., 2023, Kaiser et al., 28 Jun 2025)
Retention time	12 hours – 10 years	PCM/memresonator/dual-mode	(Tossoun et al., 2023, Kari et al., 2024)
Weight precision	up to 7 bits (14 levels)	PCM/dual-mode	(Kari et al., 2024)
Array throughput	1.5–17 PetaOps	pSRAM/WDM arrays	(Wijeratne et al., 23 Mar 2025, Arockiaraj et al., 31 Jan 2026)
Power efficiency	2.5–10 TOPS/W	pSRAM/photonic tensor core	(Kaiser et al., 28 Jun 2025, Kari et al., 2024)
Compute density	7.3–10 TOPS/mm²	pSRAM/tensor core/MZI mesh	(Kaiser et al., 28 Jun 2025, Brückerhoff-Plückelmann et al., 31 Oct 2025)
Endurance (cycles)	$10^3$–$10^8$	PCM/memristor-based	(Tossoun et al., 2023, Kari et al., 2024)

These cells and arrays are integrated in crossbar, mesh, or tensor-core architectures. Dense WDM schemes, such as those in (Wijeratne et al., 23 Mar 2025), leverage >50 parallel channels to reach aggregate terabit/s rates and compute densities far above eSRAM. Architectural efficiency is maximized when static (write-hold) power approaches zero (true for nonvolatile PCM/memristor), and dynamic energy per MAC is minimized by direct analog summation and optical fan-in.

A key point is the ability to decouple high-throughput, energy-efficient inference—where photonic in-memory excels—from in-situ training or reconfiguration, which accelerates in hybrid volatile/non-volatile or mixed-precision cells (Kari et al., 2024, Charalampous et al., 5 Aug 2025).

4. System-Level Integration, Hybrid Approaches, and Co-Design

State-of-the-art photonic in-memory systems combine these primitives within multilayered, heterogeneous architectures:

• Photonic tensor cores and crossbars: Arrays of pSRAM or PCM-weight banks form reconfigurable, high-throughput matrix–vector computation accelerators. Examples achieve 4.1 TOPS (3.02 TOPS/W) for a mixed-signal tensor core with integrated MRR-based ADC (Kaiser et al., 28 Jun 2025), and up to 17 PetaOps for a hyperspectral pSRAM crossbar mapped to MTTKRP tensor kernels (Wijeratne et al., 23 Mar 2025).
• Analog–digital interfacing: To realize full-system pipelines (e.g., neural inference, scientific computing), photonic in-memory cores are augmented with fast EO/OE converters, one-hot or flash ADC architectures, and electrical control circuits. System-level studies show that when memory bandwidth and conversion overhead are adequately provisioned, sustained performance can reach multi-TOPS at >2.5 TOPS/W, with sub-nanosecond latencies for crossbars and mesh arrays (Brückerhoff-Plückelmann et al., 31 Oct 2025, Arockiaraj et al., 31 Jan 2026).
• Hybrid photonic–electronic in-memory computing: Hybrid systems distribute workloads across photonic and electronic PIM tiers to optimize energy–latency–precision tradeoffs. Multi-objective frameworks such as H³PIMAP enable ~3.5× lower latency and ~2.7× higher efficiency versus homogeneous PIM mapping for vision and LLMs, by partitioning layers or weight blocks according to compute and precision requirements (Yin et al., 10 Mar 2025).
• Large model and distributed architectures: Photonic-in-memory processing elements are deployed in multi-chiplet, optically interconnected networks (PICNIC). Here, optically networked PEs (e.g., RRAM crossbars) and silicon photonic links achieve power-efficient scaling for large LLM inference, achieving up to 57× efficiency improvement over leading digital accelerators with hierarchical chiplet-cluster power gating (Chong et al., 6 Nov 2025).

5. Application Domains and Algorithmic Mapping

Photonic in-memory computing is now demonstrated in several high-impact application spaces:

• Machine learning and neural networks: Photonic ONNs and SNNs exploit in-memory PCM/weight banks for inference and in-situ on-chip training (Zhou et al., 2023, Zhu et al., 2021, Chakraborty et al., 2018), achieving close to digital-baseline accuracy on MNIST and Fashion-MNIST with <1% loss. Mixed-precision and multi-modal cells enable >12-bit precision for large matrix operations (Charalampous et al., 5 Aug 2025).
• Scientific and tensor computing: High-throughput arrays support key HPC primitives, e.g., MTTKRP for tensor decomposition, Vlasov-Maxwell equation for plasma simulations, and PDE solvers, showing constant-time acceleration versus quadratic traditional compute (Arockiaraj et al., 31 Jan 2026, Charalampous et al., 5 Aug 2025).
• Boolean and binary neural computation: Photonic logic latches and X-pSRAM arrays deliver fast, massively parallel Boolean operations (XOR, popcount), enabling cryptography and hyperdimensional computing (Kaiser et al., 28 Jun 2025).
• Neuromorphic systems: All-optical SNN primitives integrate in-memory photonic synapses and spike-based computation, exploiting WDM for MAC parallelism and achieving fJ synaptic energy and sub-ns per-operation latency (Chakraborty et al., 2018).

6. Scalability, Limitations, and Open Challenges

Current photonic in-memory platforms are subject to both device-level and systems-level scaling phenomena:

• Thermal and optical crosstalk: Dense PCM/ring integration demands mitigation of heat diffusion and resonance drift, addressed by athermal designs or active feedback (Kari et al., 2024, Wijeratne et al., 23 Mar 2025).
• Precision and variability: PCM devices intrinsically have limited multi-level linearity and endurance. Mitigation is possible via algorithm–hardware co-design (e.g., ELight, write-aware training and block matching yielding 20× dynamic energy and write reduction) (Zhu et al., 2021).
• Bandwidth and loss: WDM is constrained by comb line spacing, ring FSR, and optical insertion losses. For large matrix sizes (>100×100), power and loss scaling dominate design limits unless device innovations reduce per-cell loss or increase Q-factors (Brückerhoff-Plückelmann et al., 31 Oct 2025).
• Endurance and reconfiguration: PCM/memristor-based weights have $10^{3}$–$10^{8}$ cycle limits; dual-mode or hybrid architectures decouple frequent fine-tuning (carried by volatile electronics) from slow, coarse non-volatile weight writes (Kari et al., 2024, Charalampous et al., 5 Aug 2025).
• System-level bottlenecks: Even with photonic dataflow, opto-electronic conversion and external memory accesses remain limiting for memory-bound workloads (e.g. MTTKRP), while compute-bound workloads scale linearly with photonic array size and frequency (Arockiaraj et al., 31 Jan 2026).
• Integration complexity: Monolithic 3D stacking, photonic-electronic process integration, and hierarchical tiling—though demonstrated—pose fabrication and yield challenges for large-scale, multi-million operation arrays (Charalampous et al., 5 Aug 2025, Chong et al., 6 Nov 2025).

7. Outlook and Emerging Directions

Photonic in-memory computing is transitioning from foundational device and primitive demonstrations to heterogeneous, system-level platforms that blend the strengths of photonics and electronics across all stack layers. Moving toward multi-TOPS/W, multi-PetaOps-scale accelerators with sub-ns latency will depend on advances in device yield, high-Q low-loss resonators, robust nonvolatile memory technologies, scalable WDM sources, and algorithms codesigned with underlying photonic variability. Hierarchical and hybrid system designs, along with intelligent workload partitioning frameworks, will be pivotal. The simultaneous acceleration of AI, scientific computing, and distributed inference workloads will further drive the evolution of this domain (Kaiser et al., 28 Jun 2025, Arockiaraj et al., 31 Jan 2026, Yin et al., 10 Mar 2025, Chong et al., 6 Nov 2025).