Monolithic Integration of Piezo-Optomechanical Photonics and CMOS Electronics

Abstract: Next-generation photonic architectures for AI, sensing, and quantum computing require thousands to millions of reprogrammable photonic devices on a chip[1]. The monolithic integration of Electronically-backed Photonic Integrated Circuits (EPICs) allows for very high density electrical interconnection and electronic drivers that can scale with photonics. Piezo-optomechanical photonic integrated circuits (POMPICs) offer low power consumption, high speed modulation, cryogenic compatibility and broadband optical transparency from ultraviolet to infrared wavelengths[2,3], but have not been demonstrated with monolithically integrated CMOS electronics. Here, we show a fully monolithic, all-CMOS fabricated platform for POMPICs co-fabricated with commercial control electronics. 200 millimeter photonic wafers are constructed directly on completed CMOS driver wafers by back-end-of-line processing, connecting integrated piezoelectric actuators under broadband silicon nitride waveguides to a high-density digital backplane comprising >2 million electrical connections per die with 6.4x6.4 micron electrode pitch. We introduce segmented POMPIC components as Photonic Digital-to-Analog converters (PDACs) that convert low-voltage digital electronic signals to multi-bit analog optical phase and amplitude modulation, and we demonstrate parallel control of optical phase shifters, Mach-Zehnder interferometers, optical routing trees, and tunable ring resonators using a standard HDMI interface to program CMOS electronics. We test multiple reticles and perform electronic and photonic characterization across the entire wafer to establish uniformity and yield, demonstrating wafer-scale integration of POMPICs on an electronic backplane and enabling dense, scalable electronic control of piezo-optomechanical circuits.

• The paper demonstrates wafer-scale monolithic integration of piezo-optomechanical photonic circuits with CMOS electronics for high-density, high-speed control.
• It utilizes BEOL fabrication on 200 mm CMOS wafers with over 2 million electrodes per die, ensuring precise lithographic alignment and robust thermal compatibility.
• Benchmarked components like MZIs and ring resonators achieved phase resolutions up to 8 bits and fast response times, promising scalable photonic and quantum computing applications.

Monolithic Integration of Piezo-Optomechanical Photonics and CMOS Electronics: A Technical Review

Introduction

The integration of photonic functionalities with electronic control is a prerequisite for the scalability of next-generation photonic information processing, quantum computing, and AI photonic hardware. The paper "Monolithic Integration of Piezo-Optomechanical Photonics and CMOS Electronics" (2607.01514) presents a comprehensive demonstration of the monolithic wafer-scale integration of piezo-optomechanical photonic integrated circuits (POMPICs) directly on commercially available CMOS backplanes. This work addresses critical technical challenges impeding the widespread deployment of large-scale, reconfigurable photonic systems by enabling dense, high-speed, cryogenically compatible, and low-power photonic control with digital precision.

Technical Advancements in Integration

The core contribution is the monolithic back-end-of-line (BEOL) fabrication of POMPICs on CMOS electronic integrated circuit (EIC) wafers, exploiting the foundry-scale manufacturing capabilities typically reserved for microdisplays. Using a 200 mm CMOS wafer equipped with more than 2 million electrodes per die at a 6.4 µm pitch, the authors establish vertical interconnects (VIAs) to drive dense arrays of AlN piezoelectric actuators underneath broadband SiNx waveguides.

The process overcomes significant hurdles:

• Lithographic Alignment: Achieving precise overlay between photonic and electronic layers to prevent device failure or electrical shorting.
• Thermal and Chemical Compatibility: Maintaining CMOS reliability following high-temperature and XeF₂ etching steps necessary for POMPIC release and AlN growth.
• Yield and Uniformity: Full-wafer electrical and optical characterization confirms high device yield and functional uniformity, with no detectable performance degradation relative to devices fabricated on blank silicon substrates.
• High-Density Actuation: The digital electrode backplane is interfaced via a vendor-supplied driver board accepting HDMI imaging data, enabling parallel, low-latency control of photonic elements using standard digital protocols.

Device Architecture and Performance

Segmented piezo-driven devices are architected as photonic digital-to-analog converters (PDACs), allowing binary-driven multi-bit analog modulation of optical phase and amplitude. The authors report several key photonic components, each benchmarked for precision, actuation speed, and modulation fidelity:

• Mach-Zehnder Interferometers (MZIs): Vertically-actuated cantilever MZIs (V-CMZIs) achieve phase resolutions up to 7 bits with extinction ratios >20 dB, 15 µs response times, and voltage-length products of ≈25 V·cm. Strain-optic MZIs (SMZIs) demonstrate even finer phase tuning (8 bits), >30 dB extinction, and similarly low capacitance.
• Ring Resonators: Both pie-wedge (P-Ring) and annular (A-Ring) geometries achieve linear and bipolar resonance tuning with segment-level actuation sensitivity of 40–250 MHz/segment. Capacitances per actuator are sub-0.1 pF, indicating inherent GHz-speed drive compatibility with custom electronics.
• Programmable Photonic Circuits: Complex configurations such as 1×4 switching trees, multi-beamsplitter interferometers, and routing meshes are digitally programmed, confirming the suitability of this architecture for photonic computation and reconfigurable quantum circuits.

The phase and amplitude modulation bit-depths are directly tied to the segment count and piezoelectric coupling efficiency, with prospects for further scaling via both analog and custom digital driver architectures.

Implications for Photonic and Quantum Systems

Practical Implications:

• Scalability: The demonstrated architecture supports >2 million electrical interconnects per die, directly addressing the bottleneck in photonic device scaling for classical and quantum systems.
• Power and Thermal Efficiency: Ultra-low drive capacitance and direct CMOS proximity reduce energy consumption. Piezo-tuned mechanisms, in contrast to thermal or electrical carrier injection, are inherently suitable for cryogenic operations (demonstrated down to <0.5 K).
• Process Compatibility: The integration leverages standard CMOS foundry flows and commercial display driver backplanes, enhancing prospects for rapid industrial adoption and further reduction in system size, weight, and cost.

Theoretical Implications:

• Quantum Photonics: The technology path is highly relevant for the construction and control of high-qubit-count linear optical quantum computers and hybrid quantum systems, including the integration of solid-state spin-photon interfaces.
• Neuromorphic and AI Photonic Architectures: High-density, reprogrammable photonic meshes with multi-bit control are a direct enabler for photonic neural networks, optical memory, and scalable photonic accelerators.

Prospects for Future Developments

• Enhanced Integration: Anticipated improvements in strain engineering, the adoption of alternative piezoelectric materials (e.g., Sc-doped AlN), and advanced actuator designs promise to raise modulation efficiency and reduce energy per operation.
• Process Development Kit (PDK) Standardization: The monolithic EIC-PIC integration is poised for incorporation into scalable PDKs with parameterized cells for design automation across photonic foundries.
• Hybrid System Expansion: Exposed waveguide layers allow for post-fabrication processing, such as laser integration, quantum emitter embedding, and detector fabrication, opening the route for full-stack quantum photonic modules.
• Application Scope: The architecture is immediately applicable to beamscanning systems, LiDAR, optical interconnects, advanced microscopy, and displays, in addition to large-scale quantum information processors.

Conclusion

This work represents a significant step in the integration of photonic and electronic platforms at wafer scale, demonstrating an all-CMOS-fabricated, monolithic POMPIC system with dense, digital, high-speed control. The demonstrated device metrics meet or exceed those of non-integrated counterparts, and the methodology resolves longstanding scaling obstacles for photonic quantum computing, programmable photonic circuits, and energy-efficient photonic AI hardware. With further advances in process engineering and hybrid integration, the platform is well-positioned for deployment in both quantum and classical information systems where high-channel-count, low-power, and high-bandwidth photonic control are mandatory (2607.01514).