Digital Time-to-Digital Converter (DTDC)

• Digital Time-to-Digital Converters (DTDCs) are circuits that decompose time into a coarse counter value and a fine interpolation, enabling high-resolution timestamping.
• They employ various digital architectures—such as carry-chain TDLs, multi-phase clocks, wave-union, and oscillator-based methods—to balance precision, throughput, and calibration complexity.
• DTDC designs integrate encoding strategies and histogram-based calibration to mitigate nonlinearity, jitter, and timing bubbles, enhancing accuracy in applications like quantum and biomedical imaging.

Digital Time-to-Digital Converter (DTDC) refers, in the reported literature, to a class of time-measurement circuits in which timestamp formation and sub-clock interpolation are carried out with digital structures such as coarse counters, multi-phase clocks, tapped delay lines, carry chains, Gray-code oscillators, and ring oscillators. Across FPGA- and ASIC-based realizations, the common abstraction is a coarse/fine decomposition of time, often expressed as $$t_{\rm meas}=N_{\rm coarse}T_{\rm clk}+t_{\rm fine}$$, with the coarse term setting dynamic range and the fine term resolving the interval within one clock period (Qin et al., 2017, Wagner et al., 2024, Park et al., 5 Nov 2025). The DTDC literature is therefore not a single architecture but a design space defined by interpolation method, encoding strategy, calibration regime, and system-level constraints such as jitter, linearity, throughput, dead time, and channel scalability (Qi et al., 2015, Martinelli et al., 2021, Wang et al., 2022).

1. Measurement model and digital timing abstraction

A recurring DTDC signal path begins with an asynchronous hit, converts it into a form suitable for digital capture, resolves the hit position within a clock period, and then combines that fine result with a free-running coarse counter. In the FPGA-based converter integrated for nitrogen-vacancy-center instrumentation, a fast comparator outputs an LVDS pulse, the pulse propagates through a carry-chain fine-delay line, D flip-flops sample the chain at 125 MHz, a 32-bit counter provides the coarse count, and a thermometer-code-to-binary encoder generates the fine word; the resulting timestamp is the pair $(N_{\rm coarse}, t_{\rm fine})$ (Qin et al., 2017). The same coarse/fine structure also appears in the steady-calibrated MARTY TDC, where a 48-bit coarse counter at $f_s=412.5$ MHz is combined with a TDL-based interpolator, and in the UltraScale+ design where the final timestamp is written as $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$ (Wagner et al., 2024, Park et al., 5 Nov 2025).

The fine measurement can be defined in several equivalent ways, depending on architecture. In carry-chain TDL converters, the fine code is derived from the number or position of propagated taps within one clock period; in the Virtex-7 implementation reported in 2017, the effective least-significant bit was approximately $23$ ps, with $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$ (Qin et al., 2017). In a multi-phase-clock DTDC, the fine term is instead determined by which phase-shifted clocks are sampled by the incoming edge; the Stratix III design using four clocks at $0^\circ$, $45^\circ$, $90^\circ$, and $135^\circ$ divides a $(N_{\rm coarse}, t_{\rm fine})$0 ns interval into eight $(N_{\rm coarse}, t_{\rm fine})$1 ps bins and measures the full interval as

$(N_{\rm coarse}, t_{\rm fine})$2

(Qi et al., 2015)

Oscillator-based DTDCs preserve the same conceptual split while replacing the static delay line. The multi-path differential ring-oscillator design in 130 nm BiCMOS estimates the event-specific delay quantum through a calibration interval,

$(N_{\rm coarse}, t_{\rm fine})$3

and then uses that calibrated $(N_{\rm coarse}, t_{\rm fine})$4 to compute time of arrival and time over threshold (Martinelli et al., 2021). The Gray-code-oscillator architecture likewise assembles a timestamp from a sampled oscillator state and a coarse counter, with

$(N_{\rm coarse}, t_{\rm fine})$5

(Wang et al., 2022)

2. Principal DTDC architectures

One major DTDC family is the multi-phase-clock or oversampling converter. The 2015 single-FPGA design based on a PLL-generated interpolation clock multiplied a 125 MHz reference by 8, produced four 50%-duty clocks with phase shifts of $(N_{\rm coarse}, t_{\rm fine})$6, $(N_{\rm coarse}, t_{\rm fine})$7, $(N_{\rm coarse}, t_{\rm fine})$8, and $(N_{\rm coarse}, t_{\rm fine})$9, and achieved a theoretical resolution of $f_s=412.5$0 ps without per-bin calibration (Qi et al., 2015). A related Virtex-5 implementation for the KLOE-2 High Energy Tagger used four phases at $f_s=412.5$1, $f_s=412.5$2, $f_s=412.5$3, and $f_s=412.5$4 from a 400 MHz clock, giving a $f_s=412.5$5 ps LSB and a measured single-hit jitter of approximately $f_s=412.5$6 ps (Iafolla et al., 2012). These architectures trade sub-10-ps granularity for low logic cost, deterministic phase generation, and modest calibration burden.

The dominant FPGA DTDC family is the tapped-delay-line converter implemented in fast carry structures. Representative examples include the Virtex-7 carry-chain TDC with $f_s=412.5$7 ps bin size (Qin et al., 2017), the Zynq-7020 MARTY channel using 36 CARRY4 blocks and 144 taps to cover a coarse period of about $f_s=412.5$8 ns with a calibrated mean LSB of $f_s=412.5$9 ps (Wagner et al., 2024), the Arria 10 design that combined four 280-tap TDLs into 921 effective bins with a mean bin width of $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$0 ps (Kuang et al., 2018), and the 64-channel Kintex-7 implementation using 100 CARRY4 slices, 400 taps, and a 400 MHz sampling clock (Liang et al., 2024). In these realizations, the FPGA carry network is repurposed as a fine interpolator, while the coarse counter extends the dynamic range from tens of seconds to about one week, depending on clock rate and counter width (Qin et al., 2017, Wagner et al., 2024).

A third family is the wave-union and multi-edge DTDC. Rather than launch a single transition into the TDL, wave-union injects multiple edges in one clock period so that several correlated fine measurements can be combined. The 64-channel Kintex-7 design used a 4-edge Wave-Union A generator, yielding an ideal multi-edge LSB of about $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$1 ps and an average calibrated LSB of approximately $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$2 ps across channels (Liang et al., 2024). The UltraScale+ bidirectional-encoder design combined four-edge WU-A, dual-sampling, and sub-TDL methods, and reported a measured LSB of approximately $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$3 ps per channel (Wang et al., 2022). The divide-and-conquer encoding work further demonstrated normal TDL, half-length delay-line, double-edge wave-union, and four-edge wave-union variants on Artix-7, with effective bin sizes of $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$4 ps, $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$5 ps, $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$6 ps, and $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$7 ps, respectively (Dong et al., 2022).

A fourth family replaces carry-chain delay sampling with oscillator state sampling. The 130 nm multi-path differential ring-oscillator DTDC achieved a 33.6 ps LSB, single-shot precision of 19.5 ps, and PLL-free event-by-event calibration (Martinelli et al., 2021). The 16-channel Gray-code-oscillator architecture, implemented on 16 nm, 20 nm, and 28 nm Xilinx FPGAs, used a sampling matrix and virtual-bin calibration method to obtain best LSB values of $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$8 ps on UltraScale+, $$t_{\rm meas}=n_{\rm coarse}T_{\rm clk}+t_{\rm fine}(b)$$9 ps on UltraScale, and $23$0 ps on Virtex-7 (Wang et al., 2022). These oscillator-based approaches emphasize low hardware consumption and resolution configurability rather than extreme sub-picosecond binning.

3. Encoding, bubble suppression, and calibration

Most TDL DTDCs first capture an imperfect thermometer code and then map it into a fine-time index. In ideal operation the code is a monotone run of ones followed by zeros, but advanced FPGA nodes exhibit “bubbles,” namely isolated inversions inside the code. The Arria 10 study states explicitly that advanced FPGAs in 20 nm and 28 nm exhibit bubbles caused by process variation, crosstalk, and jitter, and that a simple thermometer-to-binary encoder would merge bins and degrade precision (Kuang et al., 2018). That observation motivated several encoder families.

One response is ones-count encoding. In the Arria 10 implementation, the encoder counts the total number of ones in the raw tap vector instead of locating only the last one; the authors argue that a missing one changes the count by only one and preserves relative ordering (Kuang et al., 2018). A more resource-conscious response is the divide-and-conquer encoder, which partitions the raw vector into 24-bit pieces, computes local population counts and flags, forms a transition-selection vector by XORing neighboring flags, and then refines the transition index with fixed-weight arithmetic. In the Artix-7 demonstrations, this reduced LUT and FF utilization by 45% to 70% compared with traditional encoders, while the encoding dead time remained one clock cycle (Dong et al., 2022). Other encoder strategies include the real-time bidirectional encoder for four-transition pseudo-thermometer codes (Wang et al., 2022) and the online severe-bubble solution based on tap swapping around the BUFG boundary in the 64-channel Kintex-7 system (Liang et al., 2024).

A second response is to alter the sampling pattern itself. The cross-detection method reorders neighboring taps from $23$1 to $23$2, while dual-side monitoring captures both start-of-propagation and end-of-propagation thermometer codes and calibrates the former by subtracting the latter plus a fixed $23$3 LSB term. In the Virtex-7 CD-DSM implementation, the reported bubble rate fell from approximately 54% to approximately 5%, the average bin size was 6.1 ps, and the additional hardware cost of DSM was one CARRY4 (Lee et al., 2024).

Calibration in DTDCs is generally histogram-based. The code-density procedure estimates the physical width of each bin from occupancy counts. In the MARTY TDC,

$23$4

and DNL is first defined from the raw histogram and then re-expressed after calibration in time units (Wagner et al., 2024). The 2017 Virtex-7 device used a code-density calibration followed by an INL-derived look-up table that converted raw fine codes to corrected codes in real time; the reported uncorrected DNL and INL were $23$5 LSB and $23$6 LSB, respectively (Qin et al., 2017). The Gray-code-oscillator architecture generalized this idea into a Virtual Bin Calibration Method, with configurable virtual-bin resolution and compensation tables stored in BRAM (Wang et al., 2022).

Recent work extends calibration beyond static LUT equalization. The MARTY design performs steady calibration during normal operation by exploiting single-photon detections, maintaining a rolling histogram of the last $23$7 k counts per bin, and updating the calibration without interrupting acquisition (Wagner et al., 2024). The 16 nm UltraScale+ work introduced Partial Order Reconstruction, which infers the physical ordering of bins through directed acyclic graph analysis, and Iterative Time-bin Interleaving, which merges multiple calibrated TDLs into a single sorted delay basis (Park et al., 5 Nov 2025). This progression suggests that calibration has become a primary architectural dimension rather than a mere post-processing step.

4. Reported performance envelope

Reported DTDC performance spans more than three orders of magnitude in nominal bin size, from 625 ps in four-phase oversampling to sub-picosecond fine bins in wave-union and interleaved TDL designs. At the coarse end, the Virtex-5 oversampling TDC delivered 625 ps LSB, DNL of $23$8 LSB, INL of $23$9 LSB, and approximately 50 ps RMS single-hit jitter (Iafolla et al., 2012). At the fine end, the UltraScale+ bidirectional-encoder design reported a 0.47 ps LSB per channel, while the UltraScale+ POR+ITI design reported 1.15 ps resolution with 3.38 ps RMS precision and comparatively tight nonlinearity bounds of DNL $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$0 LSB and INL $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$1 LSB (Wang et al., 2022, Park et al., 5 Nov 2025).

Work	Core technique	Reported figures
(Qi et al., 2015)	PLL-based multi-phase clock	125 ps resolution; $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$2 ps and 113 ps; maximum nonlinearity 0.056%
(Qin et al., 2017)	Virtex-7 carry-chain TDL	23 ps LSB; 15 ps STD at 0.96 ns; 19 ps STD at 99.999999 ms
(Wagner et al., 2024)	Zynq TDL with steady SPD calibration	18.22 ps mean LSB; 27.11 ps jitter FWHM; up to 15 Mevents/s; about 1 week before overflow
(Kuang et al., 2018)	Four merged Arria 10 TDLs	2.17 ps mean bin width; 5.45 ps average RMS over 0–50 ns
(Lee et al., 2024)	Cross-detection + dual-side monitoring	6.1 ps average bin size; 3.8 ps RMS
(Liang et al., 2024)	64-channel 4-edge Wave-Union A	about 3 ps average LSB; 4.77 ps average RMS; maximum per-channel RMS below 8 ps
(Wang et al., 2022)	4-edge WU-A + dual-sampling + sub-TDL	0.47 ps LSB; best-case RMS 3.06 ps
(Park et al., 5 Nov 2025)	POR + ITI + bin-width calibration	1.15 ps resolution; 3.38 ps RMS; DNL $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$3; INL $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$4

Linearity metrics vary as strongly as nominal resolution. The steady-calibrated Zynq design reported pre-calibration DNL in the range $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$5 LSB and post-calibration DNL well contained within $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$6 LSB (Wagner et al., 2024). The CD-DSM Virtex-7 design reported DNL range $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$7 LSB and INL range $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$8 LSB, compared with a conventional delay-line TDC on the same FPGA showing $$N_{\rm taps}\approx 8\,\text{ns}/23\,\text{ps}\approx 350$$9 LSB and $0^\circ$0 LSB, respectively (Lee et al., 2024). By contrast, the UltraScale+ bidirectional-encoder design achieved a smaller nominal LSB but reported DNL ranges up to $0^\circ$1 LSB and INL ranges up to $0^\circ$2 LSB (Wang et al., 2022). This indicates that LSB, RMS precision, and nonlinearity are partially independent axes of DTDC quality.

Dynamic range and throughput are determined chiefly by the coarse counter, buffering, and transport path. The Virtex-7 integrated device combined 23 ps fine bins with a dynamic range of about 34 s from a 32-bit counter at 125 MHz, with 42 s reported for a 33-bit counter (Qin et al., 2017). MARTY used a 48-bit coarse counter at 412.5 MHz, enabling about one week of operation before rollover and continuous streaming up to 12 Mevents/s without overflow, with architecture proven up to 15 Mevents/s (Wagner et al., 2024). The 64-channel Kintex-7 WU-A converter reported a wave-generator dead time of 7.5 ns, an additional 10 ns encoder delay, and a worst-case dead time of 17.5 ns, corresponding to approximately 57 MS/s per channel (Liang et al., 2024).

5. System integration and application domains

DTDCs are frequently embedded in larger digital instruments rather than deployed as isolated timing cores. The Virtex-7 device designed for nitrogen-vacancy-center applications integrated two arbitrary-waveform-generator channels operating at 1 Gsps with maximum bandwidth of 500 MHz, twelve pulse channels with 50 ps time resolution in duration and delay, a 23 ps FPGA-based TDC, and a data accumulation module able to record count rate and time-measurement distributions (Qin et al., 2017). The same work emphasizes modular hardware organization across a digital FPGA compartment, an analog DAC board, and a pulse-driver board, and identifies applicability to quantum technologies based on N-V centers, quantum dots, phosphorus doped in silicon, and defect spins in silicon carbide (Qin et al., 2017).

Quantum communication is another explicit DTDC application domain. The MARTY TDC was tested in a QKD setup in which Alice emitted an “HVDD” polarization-encoded sequence at 1550 nm and Bob timestamped four SPD outputs with MARTY and a commercial QuTAG. The measured detected-pulse widths were approximately 115 ps for MARTY and approximately 100 ps for QuTAG, both dominated by SPD jitter of about 100 ps, while the QBER was approximately 2.2% for both devices (Wagner et al., 2024). The reported significance is operational: steady single-photon-based calibration avoids halting data acquisition and avoids interpolation-based recalibration losses, which is described as crucial for satellite-link QKD with short acquisition windows (Wagner et al., 2024).

In high-energy physics, DTDCs are integrated with trigger and DAQ logic. The KLOE-2 High Energy Tagger used a Virtex-5 FPGA with 32 channels, a 625 ps DTDC, an embedded acquisition chain, and a zero-suppression algorithm that reduced the raw TDC data rate by a factor of 20 because only about 20% of the 120 DA$0^\circ$3NE bunches contained particles (Iafolla et al., 2012). The NA62 experiment at CERN used TDC-based mezzanine boards hosting four HPTDC chips each, giving 128 channels per TDCB and 512 channels per TEL62 carrier. The HPTDC timestamp had nominal 98 ps LSB from 25 ns/256 subdivision, board-level tests measured approximately 61 ps RMS on a fixed 25 ns interval, and the TEL62 firmware framed data every 6.4 $0^\circ$4s to avoid ambiguity from the 51.2 $0^\circ$5s HPTDC rollover (Pedreschi et al., 2014).

Biomedical timing is represented by the CD-DSM work. Two identical CD-DSM TDC channels were used with CRI-MCP-PMT detectors viewing a $0^\circ$6Na point source, and the coincidence timing resolution was 98 ps FWHM, compared with 97 ps FWHM measured by an oscilloscope (Lee et al., 2024). The UltraScale+ bidirectional-encoder design explicitly identifies particle physics, biomedical imaging such as PET, and general-purpose scientific instruments as target domains (Wang et al., 2022).

6. Design trade-offs, misconceptions, and active directions

Several trade-offs recur across DTDC architectures. In the 2017 Virtex-7 design, a slower 125 MHz system clock reduced the number of required taps per 8 ns while preserving long dynamic range, whereas a finer LSB would require proportionally more delay taps or faster carry elements (Qin et al., 2017). The 64-channel Kintex-7 WU-A work formulates analogous trade-offs more generally: higher $0^\circ$7 lowers LSB but increases clock-jitter impact and routing difficulty; more injected edges $0^\circ$8 improve precision by approximately $0^\circ$9 but increase encoder complexity and dead time; and larger TDL length improves base resolution but consumes more slices and increases skew and bubbles (Liang et al., 2024). The Arria 10 study similarly notes that bubble density grows with finer-granularity carry chains and that LUT injection adds about 2 ps RMS jitter compared with Xilinx counterparts (Kuang et al., 2018).

A common misconception is that reported LSB alone is sufficient to characterize DTDC quality. The literature does not support that simplification. The UltraScale+ bidirectional-encoder work reported a 0.47 ps LSB but also DNL up to $45^\circ$0 LSB and INL up to $45^\circ$1 LSB (Wang et al., 2022), whereas the UltraScale+ POR+ITI design reported a 1.15 ps resolution together with 3.38 ps RMS precision and much tighter DNL and INL bounds (Park et al., 5 Nov 2025). A plausible implication is that fine-bin count, per-bin regularity, and calibration stability can matter as much as nominal bin width.

Another misconception is that FPGA-based DTDCs are intrinsically inferior to ASICs. The 2024 MARTY paper states that FPGA-based TDCs are a viable alternative to ASIC ones once the nonlinear behaviour due to the intrinsic nature of the device is properly mitigated (Wagner et al., 2024). At the same time, the NA62 TDCB system illustrates persistent ASIC advantages in dense channel integration and on-chip trigger matching, since each HPTDC provides 32 LVDS channels, leading and trailing edge measurement, and internal buffering hierarchy (Pedreschi et al., 2014). The literature therefore presents FPGA DTDCs and ASIC TDCs less as mutually exclusive categories than as points on a spectrum of flexibility, calibration burden, buffering capability, and integration density.

Current directions in DTDC research are concentrated in calibration and scalable digital post-processing. Reported directions include steady calibration based on single-photon detections (Wagner et al., 2024), hardware-independent post-processing through Partial Order Reconstruction and Iterative Time-bin Interleaving (Park et al., 5 Nov 2025), cross-detection with dual-side monitoring for linearly improved thermometer capture (Lee et al., 2024), resource-efficient one-cycle divide-and-conquer encoding (Dong et al., 2022), resolution-configurable virtual-bin calibration in Gray-code-oscillator TDCs (Wang et al., 2022), and PLL-free event-by-event self-calibration in ring-oscillator converters intended for massive parallelization (Martinelli et al., 2021). Taken together, these works show that DTDC development has shifted from isolated interpolation tricks toward complete digitally managed timing systems in which encoder topology, calibration flow, and application context are co-designed.