Closed-Loop FPGA Recalibration

• The protocol is a hardware-based calibration loop that integrates measurement, inference, and actuation entirely on FPGA, eliminating host-computer delays.
• It employs techniques such as Analytical Decay Estimation (ADE), Sparse Phase Estimation (SPE), and golden-section search to optimize key parameters in real time.
• By reducing latency and mitigating drift in superconducting qubits, the approach improves gate fidelity and preserves coherence during continuous recalibration cycles.

A closed-loop on-FPGA recalibration protocol is an end-to-end control methodology in which measurement generation, acquisition, inference, optimization, and parameter update are co-located on FPGA-resident control hardware, so that newly estimated parameters can be consumed by the next control action or experiment without CPU round trips. In the most explicit recent formulation, the protocol is motivated by the observation that superconducting qubit parameters drift on sub-second timescales and therefore require calibration and benchmarking primitives that execute on millisecond timescales (Marciniak et al., 12 Feb 2026). Closely related implementations appear across FPGA-based qubit control, time-to-digital conversion, transceiver synchronization, microwave LLRF, and mixed-signal conversion, where the same structural pattern recurs: an on-chip sensing path estimates a drift or state error, and a local actuator or lookup-table update applies the correction before host-side software would ordinarily return a decision (Gebauer et al., 2019, Bourdeauducq, 2013, Xie et al., 2018, Zhu et al., 2023, Li et al., 27 Nov 2025).

1. Definition and scope

In its strict sense, the protocol closes the calibration loop inside the control hardware itself. The canonical sequence is: choose sampling points around the current estimate, execute the measurement, average or classify shots on FPGA, infer a parameter analytically or by onboard optimization, update the control parameter immediately, and proceed to the next experiment. In the superconducting-qubit implementation on Quantum Machines OPX1000 hardware, this stack includes pulse generation, measurement acquisition, randomization or sequence generation, parameter estimation, optimization, and feed-forward, all on the same FPGA-based platform (Marciniak et al., 12 Feb 2026).

This meaning is narrower than the broader category of FPGA-assisted calibration. SoC-FPGA control frameworks can place time-critical data-plane processing in programmable logic while moving configuration, calibration, and slow control into an embedded processor or even a remote gRPC client. That arrangement supports iterative optimization, but it does not by itself constitute a fully on-FPGA recalibration loop. The distinction is operational rather than semantic: the latency-critical measure-analyze-update path either remains inside the FPGA-resident chain or traverses software and network layers (Karcher et al., 2020).

A plausible implication is that the defining property of the protocol is not a specific estimator or optimizer, but the elimination of host-computer latency from the inner loop. The details of the estimator can vary substantially across domains, whereas the architectural criterion remains constant.

2. Architectural basis and latency regime

The protocol depends on a compact hardware chain in which sensing, signal conditioning, state or parameter extraction, and actuation are contiguous. In the fluxonium-qubit control platform, the readout tone, digitization, real-time demodulation, classification, and conditional pulse generation all occur on the same FPGA-based instrument, without external computers or slow instrument handshakes. The measured platform latency is $428\,\mathrm{ns}$, defined as the delay between the last sample of the readout pulse entering the platform and the first sample of the output pulse conditioned on the acquired information. This latency is internal to the electronics and excludes cable delay and the readout-pulse duration itself (Gebauer et al., 2019).

The same architectural principle appears in continuous background compensation. In the Spartan-6 time-to-digital converter core, startup calibration initializes a lookup table from a histogram of uniformly distributed calibration events, while online calibration periodically measures a nearby ring oscillator and rescales calibrated timestamps according to

$R(n)=\frac{f_0}{f}\cdot R_0(n).$

Because this update occurs without disruption of normal event capture, the calibration loop becomes a background correction path rather than a separate downtime phase (Bourdeauducq, 2013).

A further variant is direct measurement-and-actuation closure. In the Ultrascale Kintex transceiver synchronization system, a carry8-based TDC measures lane-to-lane skew, and a tunable phase interpolator in the selected slave channel is stepped until the measured skew reaches a preset target. One channel serves as master, slave channels are selected through a MUX, and the loop repeats after each power-up or reset because the initial skew is random (Xie et al., 2018).

Across these examples, the same condition recurs: the correction must arrive on a timescale set by device dynamics or reset-induced nondeterminism, not by software turnaround. This suggests that the protocol is best understood as a latency discipline imposed on calibration, not merely as a convenience feature.

3. On-FPGA inference and optimization primitives

The most developed realization of the protocol couples sparse sampling with FPGA-resident inference. For exponential decays such as $T_1$, the calibration workflow uses Analytical Decay Estimation (ADE), a three-point estimator built from

$$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$

sampled at

$\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$

and reduced through the ratio

$$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$

For sinusoidal response functions, Sparse Phase Estimation (SPE) samples at the current estimate and at the maximally sensitive points $\theta_0\pm \pi/2$, which cancels unknown amplitude and offset terms and yields a direct phase estimate. Readout optimization is formulated as a two-dimensional search over readout detuning and amplitude, using the onboard objective

$$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$

with $\boldsymbol{\mu}_k=(\overline I_k,\overline Q_k)$, and a classifier

$$d_k^2(\mathbf{x})=\frac{(I-\overline I_k)^2+(Q-\overline Q_k)^2}{\sigma_k^2},\qquad \hat{k}=\arg\min_{j} d_j^2(\mathbf{x}).$$

The same hardware also runs golden-section search for spectroscopy peak finding and ADE-based Clifford randomized benchmarking with

$R(n)=\frac{f_0}{f}\cdot R_0(n).$0

All of these primitives are executed without offloading the fit or optimization to a host processor (Marciniak et al., 12 Feb 2026).

Primitive	Target quantity	Reported time
ADE	$R(n)=\frac{f_0}{f}\cdot R_0(n).$1 estimation	$R(n)=\frac{f_0}{f}\cdot R_0(n).$2
SPE	Pulse-amplitude calibration	$R(n)=\frac{f_0}{f}\cdot R_0(n).$3
Nelder–Mead	Readout parameter optimization	$R(n)=\frac{f_0}{f}\cdot R_0(n).$4
Golden-section search	Spectroscopy peak finding	$R(n)=\frac{f_0}{f}\cdot R_0(n).$5
ADE-based CRB	Clifford randomized benchmarking	$R(n)=\frac{f_0}{f}\cdot R_0(n).$6

The reported timing decomposition clarifies why these methods are paired with on-FPGA execution. Measured round-trip latency to a separate computer is $R(n)=\frac{f_0}{f}\cdot R_0(n).$7 over WiFi and $R(n)=\frac{f_0}{f}\cdot R_0(n).$8 over LAN, whereas onboard analysis contributes only about $R(n)=\frac{f_0}{f}\cdot R_0(n).$9 on average. The dominant cost of an offloaded workflow is therefore communication and data transfer rather than arithmetic (Marciniak et al., 12 Feb 2026).

4. Superconducting-qubit realization and long-duration operation

The continuous closed-loop protocol demonstrated on a flux-tunable superconducting transmon alternates benchmarking and recalibration. A cycle consists of baseline Clifford randomized benchmarking to measure $T_1$0, a calibration pass comprising Ramsey spectroscopy with SPE for drive-frequency calibration together with $T_1$1- and $T_1$2-pulse amplitude calibration, a $T_1$3 estimate with ADE, and post-calibration randomized benchmarking to measure $T_1$4. The in-loop calibration latency is reported as $T_1$5, and the full cadence per calibration/benchmark cycle is $T_1$6 (Marciniak et al., 12 Feb 2026).

The protocol was run continuously for $T_1$7 hours, completing $T_1$8 calibration loops. Gate error was tracked through $T_1$9. Relative to a static baseline calibration, continuously recalibrated operation yielded a $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$0 reduction in average gate infidelity and remained consistently better than the baseline initial calibration throughout the run (Marciniak et al., 12 Feb 2026).

The reported correlation analysis is notable because it distinguishes coherence-linked limitations from control-parameter drift. The drift channels analyzed were the relaxation rate $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$1, drive-frequency detuning $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$2, $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$3-pulse amplitude $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$4, and $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$5-pulse amplitude $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$6. Under recalibration, the correlation between gate error and $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$7 increased relative to baseline, while the correlations between gate error and $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$8, $$P_{\ket{1}}(t)=A e^{-\Gamma_1 t}+C,\qquad \Gamma_1=1/T_1,$$9, and $\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$0 decreased. The stated interpretation is that recalibration preserves coherence-linked performance while suppressing the influence of detuning and amplitude drift (Marciniak et al., 12 Feb 2026).

This realization also sharpens the practical meaning of “closed loop.” The loop is not merely a sequence of fast estimators. It is a calibration-and-validation cycle in which the result of one primitive becomes the input condition for the next, with no host-mediated synchronization barrier between them.

5. Related embodiments in adjacent FPGA systems

Several earlier and parallel FPGA systems instantiate close equivalents of the same protocol, even when they do not use the exact phrase “closed-loop on-FPGA recalibration protocol.” They differ primarily in what is being tracked and what actuator closes the loop.

Domain	Closed-loop mechanism	Reported result
Fluxonium qubit control	Real-time IQ classification followed by conditional $\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$1-pulse reset	$\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$2 platform latency; reset fidelity $\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$3 (Gebauer et al., 2019)
Spartan-6 TDC	Ring-oscillator-tracked LUT rescaling during operation	$\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$4 RMS over $\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$5 to $\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$6 (Bourdeauducq, 2013)
GTH transceiver synchronization	TDC measurement plus PI adjustment until preset skew target	$\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$7 RMS; maximal variation $\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$8 (Xie et al., 2018)
FEL LLRF reference tracking	Complex multiplication for point-by-point phase subtraction	$\tau\in\{t_0,\;t_0+\Delta t,\;t_0+3\Delta t\},$9 FPGA cycles versus $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$0 for CORDIC; phase RMS $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$1 with algorithm (Zhu et al., 2023)
Modulo ADC	Comparator-driven FSM, DAC feedback, under-compensation calibration, WAIT-state settling control	Dynamic-range expansion $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$2 within $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$3 bandwidth (Li et al., 27 Nov 2025)

These systems collectively show that the correction target can be a qubit state population, a tapped-delay-line transfer function, inter-lane skew, microwave reference phase, or an analog folding step. The common structure is still measure, infer, and actuate on the FPGA or within a tightly coupled FPGA-centered chain.

The fluxonium implementation is especially relevant as an antecedent in quantum control. There, the protocol uses an $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$4 readout pulse, real-time IQ extraction with a linear discriminant in the IQ plane, and a conditional $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$5 pulse if the measured state is $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$6. The full readout-and-drive sequence is approximately $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$7, compared with a passive relaxation time $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$8, and the excited-state population is reduced from $$c(t_0,\Delta t)=\frac{P_{\ket{1}}(t_0+3\Delta t)-P_{\ket{1}}(t_0)}{P_{\ket{1}}(t_0+\Delta t)-P_{\ket{1}}(t_0)}.$$9 before reset to $\theta_0\pm \pi/2$0 after reset (Gebauer et al., 2019). This is not a drift-tracking recalibration loop in the later transmon sense, but it demonstrates the same requirement that state estimation and conditional correction must complete on electronics timescales rather than on qubit-lifetime timescales.

6. Limits, trade-offs, and terminological boundaries

A common misconception is that any FPGA-associated calibration routine is equivalent to a closed-loop on-FPGA recalibration protocol. The control framework built on Zynq UltraScale+ MPSoCs illustrates the boundary case. It explicitly assigns time-critical sample-by-sample processing to programmable logic, while configuration, calibration, and iterative optimization are intended to run in software on the embedded processor. The measured access numbers show why this distinction matters: endpoint API register access has read+write latency $\theta_0\pm \pi/2$1, whereas client access via Ethernet/gRPC has read+write latency $\theta_0\pm \pi/2$2; local I$\theta_0\pm \pi/2$3C read+write is $\theta_0\pm \pi/2$4, and remote client I$\theta_0\pm \pi/2$5C read+write is $\theta_0\pm \pi/2$6 (Karcher et al., 2020). The framework is well suited to local iterative calibration, but it does not by itself imply an FPGA-only inner loop.

A second misconception is that lower delay is uniformly beneficial. In the LLRF reference-tracking algorithm, replacing CORDIC-based demodulation with complex multiplication reduces computational delay from approximately $\theta_0\pm \pi/2$7 clock cycles to $\theta_0\pm \pi/2$8, but it also causes irrelevant amplitude noise overlap and increases amplitude measurement noise. Over a one-hour comparison on CH1, phase stability RMS improves from $\theta_0\pm \pi/2$9 to $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$0, while amplitude stability RMS worsens from $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$1 to $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$2 (Zhu et al., 2023). Low-latency recalibration therefore remains a design trade-off rather than an unconditional improvement.

A third terminological issue concerns what counts as “recalibration.” In the Spartan-6 TDC, startup calibration and online calibration are distinct: startup histogramming interrupts normal operation, whereas ring-oscillator-based compensation updates the lookup table without dead time (Bourdeauducq, 2013). In the satellite-control solver, by contrast, the closest analogue is a reconfiguration-and-validation loop over fixed-point word length and PL voltage rather than an online adaptive estimator update. The reported comparison among $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$3-bit, $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$4-bit, and $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$5-bit configurations shows that lower precision reduces power but can introduce oscillations or instability; $$\mathrm{SNR}\equiv \frac{\left\lVert \boldsymbol{\mu}_1-\boldsymbol{\mu}_0\right\rVert}{\sqrt{\sigma_0^2+\sigma_1^2}},$$6-bit fixed point is described as providing a better trade-off in terms of power and system stability (Hamadouche et al., 2024). In WAND, the closed loop is responsive neuromodulation with on-board artifact cancellation and threshold-triggered stimulation, but the demonstrated in vivo controller uses a fixed threshold policy rather than a learned adaptive controller (Zhou et al., 2017).

Taken together, these cases suggest that the term “closed-loop on-FPGA recalibration protocol” spans a family of architectures rather than a single algorithmic template. What unifies them is hardware-local closure of the estimate-to-correction path; what varies is whether the loop updates a physical control amplitude, a phase reference, a timestamp lookup table, a transceiver phase interpolator, or a benchmarked qubit parameter.