Temporal Distribution Characterization (TDC)

• Temporal Distribution Characterization (TDC) is the process of measuring and digitally encoding the timing of discrete events using high-precision Time-to-Digital Converters.
• TDC systems leverage architectures like ring oscillators, Vernier delay lines, and FPGA-based techniques to achieve resolutions from ~10 ps to 312.5 ps with rigorous calibration.
• Applications include particle physics, PET/TOF imaging, neutron spectroscopy, and high-rate RPC experiments, enabling detailed temporal analysis and event reconstruction.

Temporal Distribution Characterization (TDC) refers to the precise measurement and quantification of the temporal structure of discrete physical events, most commonly employing Time-to-Digital Converters (TDCs) to digitize and encode arrival times. This capability is fundamental in domains such as particle physics, time-of-flight (TOF) positron emission tomography (PET), neutron TOF spectroscopy, and high-rate Resistive Plate Chamber (RPC) experiments. TDC-based systems capture, buffer, and digitally encode the time intervals between event triggers or the absolute time stamps of physical processes, yielding datasets suitable for constructing event time spectra, evaluating coincidence resolutions, and enabling statistical analyses of temporal distributions.

1. Principles and Architectures of Time-to-Digital Conversion

TDCs are specialized circuits that resolve time intervals or event arrival times into digital words with sub-nanosecond—often picosecond—precision. The architectural foundations of TDCs fall broadly into several categories, including ring oscillator phase interpolators, Vernier delay lines, tapped delay lines with wave-union launching, and oversampling-based FPGA implementations.

• Ring Oscillator TDCs employ multiphase ring-VCOs (e.g., 7-stage ring providing 14 phases) combined with synchronous counters to partition input intervals into fine and coarse components. The least significant bit (LSB) is dictated by the oscillator frequency and number of phases, yielding $∆t = 1/(14·F_{VCO})$. Sub-25 ps LSB and overall timing error $<25$ ps are achievable with SiGe-BiCMOS ASICs (Bruno et al., 2018).
• Vernier Delay-Line TDCs employ two delay chains with slightly different delays per stage, so the time interval is determined from the stage where a "start" edge overtakes the "stop" edge. The LSB is $|Δτ_1 - Δτ_2|$ (e.g., 25 ps for $(102.7-77.7)$ ps delays in 45 nm CMOS) (Ozdemir et al., 2020).
• Tapped Delay-Line (Wave Union) TDCs in FPGAs use carry chains to propagate pulse edges and multi-tap encoders to resolve events within a clock window. Segmenting delay lines and employing bubble suppression allows >300 effective bins per clock cycle ($\sim$10.9 ps LSB at 200 MHz), with calibration enabling consistent sub-20 ps inter-channel precision (Bryce et al., 6 Dec 2024).
• Multi-phase Oversampling TDCs utilize phase-shifted clocks (e.g., 16 equidistant 200 MHz clocks) or asynchronous input oversampling to achieve bin widths such as 100 ps in Kintex-7 FPGA implementations (Finogeev et al., 2023, Deng et al., 2018).

Implementation choices depend on the required temporal resolution, event rate, system power budget, and trade-offs among complexity, calibration effort, and radiation/environmental tolerance.

2. Temporal Resolution, Sources of Uncertainty, and Dynamic Range

The temporal performance of TDC-based TDC systems is governed by the quantization granularity (LSB size), inherent jitter sources, and nonlinearity of delay elements. In advanced ASICs, LSBs as low as 24–25 ps ($F_{VCO}=3$ GHz, 14 phases; or Vernier chain $\Delta\tau = 25$ ps (Ozdemir et al., 2020)) are common. Wave-union FPGA TDCs achieve 10.9 ps resolution via segmented-carry logic and dynamic calibration (Bryce et al., 6 Dec 2024); multi-phase clocking gives 100–312.5 ps bins depending on frequency and phase multiplicity (Finogeev et al., 2023, Deng et al., 2018). Table 1 summarizes representative figures of merit.

Architecture	Resolution (LSB)	INL/DNL	Dynamic Range
SiGe-BiCMOS ring osc.	24 ps	<±1 LSB	85 ns (8-bit counter)
45nm CMOS Vernier	25 ps	Not specified	$\sim$5 ns (N=64 taps)
FPGA Wave Union	10.9 ps	±3/1.13/–0.77 LSB	5 ns window (repeated)
FPGA 16-phase clock	312.5 ps	negligible	327 µs (16-bit counter)
FPGA asynchronous (Kintex-7)	100 ps	±20 ps RMS	Determined by counter

Jitter contributions arise from VCO phase noise (15 ps for SiGe-BiCMOS (Bruno et al., 2018)), discriminator timing (20 ps typical), quantization (LSB/$\sqrt{12}$ RMS), and systematic sources (e.g., PLL phase drift, supply and temperature dependence, carry-chain PVT sensitivity). Counter-based TDCs extend dynamic range arbitrarily, limited by word size and buffer depth, while oscillator or delay-line TDCs require careful treatment of wrap-around and calibration.

3. Calibration, Linearity, and Environmental Compensation

Calibration corrects for time-bin non-uniformities (DNL/INL), skew between channels, supply/temperature drift, and variable propagation delays. Methods include:

• Direct-Measurement ("Anchor"): Inject known programmable delays and measure raw codes to build bin-width histograms and code-to-time maps, with $<$1 ps statistical precision if a dithered reference is available (Bryce et al., 6 Dec 2024, Schug et al., 2018).
• Code-Density (Histogramming): Accumulate TDC code occurrences during uniform or random input, then deduce bin widths proportional to frequency (Bryce et al., 6 Dec 2024, Finogeev et al., 2023).
• Environmental Compensation: Characterize delay vs. voltage/temperature; Lattice CertusPro-NX shows 0.22%/mV core sensitivity and 2.5 ps INL drift per 5°C (Bryce et al., 6 Dec 2024). Routine self-calibration or on-chip thermometry triggers recalibration.

Per-channel or per-bin lookup tables (LUTs) apply in real time to correct timestamps. Integral and differential nonlinearities can be suppressed below ±1 LSB after calibration (Deng et al., 2018). Phase alignment routines adjust for inter-bank or inter-line clock skew in multi-channel FPGAs (Finogeev et al., 2023).

4. System Integration, Channel Multiplexing, and Readout

TDC-based temporal distribution characterization systems scale from few to thousands of parallel channels, with approaches varying by platform:

• ASIC Front-Ends: SiGe-BiCMOS chains incorporate pre-amplifier, discriminator, TDC, and serializer on one die, delivering per-channel power 2–3 mW and latency $<$10 ns from event to serialized output (Bruno et al., 2018).
• Multi-Channel FPGAs: Implementation in Virtex-6 or Kintex-7 supports 16–84 channels per FPGA bank, with event buffering (e.g., 512-depth ping-pong buffers), time tagging, Gigabit Ethernet readout, and real-time configuration (Deng et al., 2018, Finogeev et al., 2023). Synchronization across FPGAs uses reference clocks or White Rabbit time protocols.
• Event Record Formats: Time stamps include fine and coarse counts, validity flags, and trigger counts; serialized via parallel-in/serial-out (PISO) at rates up to 1.1 Gb/s (Bruno et al., 2018, Bryce et al., 6 Dec 2024).
• Data Aggregation: Event packets are streamed to DAQ servers for histogram construction, coincidence detection, and higher-level temporal spectrum analysis (Finogeev et al., 2023).

Dead time is determined by buffer structure and serialization; e.g., alternating serializers minimize TDC dead time for high-rate RPCs (Bruno et al., 2018), while deep channel buffers support burst capture (Deng et al., 2018).

5. Applications in Temporal Distribution Measurements

TDC-based temporal distribution characterization underpins a diverse range of scientific instrumentation:

• Muon Spin Rotation (μSR) Spectrometers measure positron time spectra with sub-300 ps resolutions, enable flexible event selection, and perform real-time calibration via Ethernet control (Deng et al., 2018).
• PET/TOF Imaging relies on TDCs to resolve inter-photon time differences for $<200$ ps coincidence resolving time (CRT), mapping to spatial localization accuracy of several mm. Vernier architectures achieve 25 ps LSBs (translating to 3.8 mm PET resolution), while practical ASICs and FPGAs deliver CRT FWHM as low as 195 ps (Schug et al., 2018, Ozdemir et al., 2020).
• High-Rate RPC and Neutron TOF Detectors require sub-25 ps single-edge precision, radiation-hardness (up to 500 kGy/$10^{15}$ n/cm$^2$), and event rates over 1 MHz/channel. Multi-GHz readout and low event-processing latency are essential (Bruno et al., 2018, Bryce et al., 6 Dec 2024, Finogeev et al., 2023).
• Spaceborne and Accelerator Instrumentation leverage radiation-tolerant TDCs in, e.g., Lattice CertusPro-NX FPGAs for time-of-flight discrimination at high event densities, with sub-20 ps inter-channel timing (Bryce et al., 6 Dec 2024).

6. Performance Metrics and Representative Measurements

Temporal distribution characterization systems specify performance in terms of LSB size, FWHM or rms timing resolution, nonlinearity, dynamic range, power per channel, and environmental robustness. Table 2 collates key achieved figures from representative systems.

System (Paper)	LSB (ps)	Single Edge Resolution (ps)	Max Event Rate	Key Features
SiGe-BiCMOS RPC TDC (Bruno et al., 2018)	24	<25	multi-GHz	8-reg depth, <10 ns latency
Vernier CMOS (PET) (Ozdemir et al., 2020)	25	n/a (simulated)	n/a	1.63 mW/channel, 5 ns range
FPGA Wave Union (Bryce et al., 6 Dec 2024)	10.9	20 (inter-ch, 1σ)	>1 MHz/ch	Radiation-hardened, rapid self-cal
Kintex-7 TOF TDC (Finogeev et al., 2023)	100	42 (gen), 146 (scint)	n/a	2000+ channels, White Rabbit sync
μSR Virtex-6 (Deng et al., 2018)	312.5	<273 (FWHM)	n/a	512-buffer/ch, per-ch calibration
TOFPET2 ASIC (Schug et al., 2018)	~30	CRT FWHM = 195–230	n/a	Dual-discriminator, fine delay ctrl

INL/DNL after calibration is typically below ±1–3 LSB. Temperature drifts of bin width are below 2.5 ps/5°C in advanced FPGAs (Bryce et al., 6 Dec 2024). Radiation tolerance of 100 krad (Lattice FPGA) and $10^{15}$ n/cm$^2$ (SiGe-BiCMOS) are validated (Bryce et al., 6 Dec 2024, Bruno et al., 2018).

7. Limitations, Optimization, and Prospects

Current TDC architectures face limitations related to bin quantization, drift from PVT (process, voltage, temperature) parameters, event buffer depth, and serialization dead time. Fine-tuning supply regulation, on-the-fly calibration, and thermal compensation help maintain temporal stability. Embedded DNL/INL correction in on-chip LUTs eliminates post-processing latency (Finogeev et al., 2023). Multi-phase clock or phase interpolator TDC architectures offer paths toward sub-50 ps bin resolution. System-level improvements include direct input topologies to minimize jitter, dynamic recalibration to address temperature drift, and the use of higher-speed SAR/waveform sampling ADCs for interpolated edge timing.

Efforts continue to extend dynamic range without sacrificing fine timing, balance channel density vs. power constraints, and ensure robustness under high-radiation or adverse environmental conditions. The trend is toward self-calibrating, radiation-hard, FPGA- or ASIC-based TDCs supporting thousands of channels, sustaining high event rates, and providing precision temporal distribution characterization suitable for next-generation high-rate experiments and advanced imaging modalities.

References: (Bruno et al., 2018, Bryce et al., 6 Dec 2024, Deng et al., 2018, Schug et al., 2018, Ozdemir et al., 2020, Finogeev et al., 2023)