Iterative Time-bin Interleaving (ITI)

• Iterative Time-bin Interleaving (ITI) is a digital technique that interleaves calibrated delay bins from multiple TDLs to enhance the resolution of FPGA-based TDCs.
• It achieves sub-2 ps resolution by merging outputs from parallel TDLs, significantly reducing both differential and integral nonlinearities.
• ITI integrates with Partial Order Reconstruction to enable scalable, high-performance time measurements without additional analog hardware.

Iterative Time-bin Interleaving (ITI) is a purely digital, hardware-independent post-processing technique that enhances the time resolution of FPGA-based Time-to-Digital Converters (TDCs). By interleaving calibrated bins from multiple parallel Tapped Delay Lines (TDLs), ITI constructs a unified, finer-grained delay chain without analog averaging, interpolation, or redundant on-chip resources. This digital bin-merging enables sub-2 ps resolution, substantially reduces Differential Nonlinearity (DNL) and Integral Nonlinearity (INL), and supports scalable high-performance TDC implementations within programmable logic devices (Park et al., 5 Nov 2025).

1. Underlying Principles and Motivation

Traditional TDCs implemented on FPGAs leverage a single TDL, where resolution is dictated by the minimum achievable delay between logic taps, typically limited to 6–10 ps for a 16 nm Xilinx UltraScale+ FPGA. This constraint arises from device-level granularity and routing variability. Iterative Time-bin Interleaving was introduced to overcome this physical bottleneck by merging bins from multiple, independently calibrated TDLs. The process is exclusively digital and post-processing: ITI requires only standard TDL output and bin-wise calibration data, not additional analog hardware or external calibration sources.

The key innovation lies in increasing the total number of effective bins by constructing a merged, globally time-ordered sequence, thus decreasing the Least Significant Bit (LSB) bin width for the unified chain. ITI’s ability to scale the effective resolution by a factor proportional to the number of contributing TDLs, subject to outlier filtering, provides a direct competitive advantage in precision time measurement and delay calibration (Park et al., 5 Nov 2025).

2. Algorithmic Structure and Formulation

The ITI procedure operates on bin timing and width data previously corrected by Partial Order Reconstruction (POR). Each TDL provides a vector of calibrated start times $t_m[j]$ and bin widths $W_m[j]$. ITI builds an interleaved temporal chain as follows:

1. Collect all usable bins from every TDL, filtering out ultra-narrow bins (those narrower than a threshold $\Delta_{\min}$, typically $0.2$ ps).
2. Merge these bins into a single list, sorted by calibrated starting time.
3. The bin sequence thus obtained defines a new, interleaved TDL with effective width near the arithmetic mean of the constituent bins or finer (depending on filtering and alignment of physical taps).

The process can be formally summarized as:

$$t_m[0] = 0, \quad t_m[n] = \sum_{k=0}^{n-1} W_m[k] \quad (n=1, \dots, N_m-1)$$

$$L = \mathrm{sort}\left\{ (t_m[j], m, j) \mid W_m[j] \geq \Delta_{\min} \right\}$$

$$t_u[k] = \tau_k, \quad W_u[k]= \begin{cases} \tau_{k+1}-\tau_k, & k<N_u-1 \ W_{m_k}[j_k], & k=N_u-1 \end{cases}$$

where $L = \{ (\tau_k, m_k, j_k) \}_{k=0}^{N_u-1}$, the sorted list of bins from all TDLs above the width threshold. This interleaved chain may itself be repetitively merged via ITI (hence “iterative”), but in practice, additional iterations yield marginal bin-count gains as ultra-narrow bins dominate the remainder (Park et al., 5 Nov 2025).

3. Integration with Partial Order Reconstruction (POR)

ITI’s efficacy is critically dependent on accurate calibration and ordering of raw TDL bins. Partial Order Reconstruction provides the following prerequisites:

• Code-density test data to reveal the utilized/missing code pattern for each TDL;
• DAG-based analysis yielding the partial ordering constraints among observed bins;
• Bin permutation solution identifying the correct physical sequencing;
• Calibrated bin start time and bin-width arrays, $\{ t_m[j] \}$ and $W_m[j]$ (post-POR).

ITI consumes these POR outputs directly, assembling the final interleaved chain digitally, without new measurements or hardware changes (Park et al., 5 Nov 2025). This workflow allows ITI to realize maximal bin recovery and achievable timing granularity, minimizing residual nonlinearity.

4. Resolution Scaling, Error Reduction, and Convergence

The effective resolution gain $W_m[j]$0 after ITI is dictated by the sum of all retained bins:

$W_m[j]$1

The post-ITI minimum bin width improves approximately by $W_m[j]$2 (exclusive of filtered-out bins). In practice, the improvement fraction is slightly less than $W_m[j]$3 due to the exclusion of ultra-narrow bins ($W_m[j]$4 in representative tests). After one ITI pass on four TDLs, $W_m[j]$5 (vs. the theoretical maximum of 4).

Table: Resolution and Nonlinearity Metrics

Configuration	Resolution (ps)	DNL (LSB) pk–pk	INL (LSB) pk–pk
Raw single TDL	8.40	8.60	45.50
+POR +ITI (no bin-width cal)	1.15	7.46	84.22
+POR +ITI +bin-width cal	1.15	0.67	2.82

Subsequent bin-width calibration after ITI further reduces DNL to $W_m[j]$6 LSB and INL to $W_m[j]$7 LSB. RMS precision in interval tests is 3.38 ps, with mean deviation below 1 ps over testing ranges (Park et al., 5 Nov 2025).

ITI convergence is reached when: (a) no further bins above $W_m[j]$8 are available, (b) the chain’s length increase per iteration drops below preset minimums, or (c) DNL/INL improvements fall below target fractions (e.g., 1%). Empirically, a single ITI pass is nearly always sufficient.

5. FPGA Implementation Details and Architectural Considerations

ITI is implemented primarily as an offline host-side (PC) digital post-processing sequence. The final interleaved chain and its encoding resources are mapped onto the FPGA. The process requires:

• $W_m[j]$9 parallel TDLs, each realized as a CARRY8 chain with associated D flip-flops.
• A high-fan-in priority encoder (or pipelined encoder hierarchy), covering all final interleaved bins to detect timing transitions.
• Stringent FPGA placement and routing to minimize skew and ensure all signals resolve within one clock period ($\Delta_{\min}$0 MHz $\Delta_{\min}$1 4 ns).
• Filtering of ultra-narrow bins avoids resource expenditure on impractically fine timing closure.

Scalability is linearly dependent on the number of parallel TDLs ($\Delta_{\min}$2) and their tap depths ($\Delta_{\min}$3), bounded by available FPGA fabric and the feasible fan-in of the unified encoder. No architectural modification is necessary for the TDLs themselves; the primary limit is imposed by the complexity and speed of the final merged chain encoding (Park et al., 5 Nov 2025).

6. Comparative Assessment, Practical Impact, and Applicability

Compared to prior FPGA TDC techniques, the POR+ITI approach yields:

• A reduction in effective LSB from 8.4 ps to 1.15 ps (a 7.3× increase in timing granularity).
• DNL/INL substantially collapsed after bin-width calibration (DNL $\Delta_{\min}$4 LSB; INL $\Delta_{\min}$5 LSB).
• RMS interval test precision down to 3.38 ps, with sub-ps mean accuracy across the tested interval.
• Enhanced bin recovery and utilization rates above 99% post-POR.

These results are achieved with moderate digital resource overhead and are broadly generalizable to other programmable logic TDC architectures. ITI’s purely digital nature and compatibility with offline calibration make it particularly suited to high-resolution and high-throughput time measurement systems, where analog or external interpolation is infeasible or inefficient (Park et al., 5 Nov 2025).