Time Domain to Digital Conversion (TDDC)

• TDDC is the process of converting physical time intervals like pulse widths and event timings into digital codes, enabling accurate temporal representation.
• It employs various circuit techniques such as delay-line sampling, multi-phase clocks, and carry-chain interpolation to achieve picosecond-level resolution.
• TDDC spans applications from FPGA-based high-resolution time measurements to sensor interfaces and delay–Doppler communications, emphasizing careful calibration and trade-offs.

Time Domain to Digital Conversion (TDDC) denotes conversion schemes in which the quantity of interest is first represented as a time variable—such as an event arrival time, pulse width, inter-spike interval, discharge duration, or delay–Doppler coordinate—and is then digitized. In the literature represented here, the term spans conventional Time-to-Digital Converters (TDCs) for digital pulse timing, voltage-to-time and resistance-to-time converters, asynchronous integrate-and-fire samplers, and direct conversion of communication waveforms from the time domain to a digital delay–Doppler grid (Dong et al., 2020, Ma et al., 2022, Naaman et al., 2023, Costanza et al., 22 Jul 2025, Mohammed, 2020).

1. Scope and conceptual basis

At its narrowest, TDDC is the conversion of a time interval into a digital code. In FPGA TDCs, that interval is usually the time between an input edge and a reference clock edge, decomposed into coarse and fine components. In broader time-based sensing, the same principle appears as voltage-to-time conversion, resistance-to-time conversion, or event-time encoding, where amplitude or sensor state is not digitized directly but is inferred from timing observables (Dong et al., 2020, Ma et al., 2022, Naaman et al., 2023).

Input quantity	Time-domain representation	Digital output
Leading edge of a digital pulse	Event arrival time within a clock period	Coarse/fine timestamp
Analog voltage	Comparator pulse width against a ramp	TDC-measured code
Resistance $R_m$	RC discharge time $t_m$	Clock count $N_m$
Bandlimited waveform	Spike times or inter-spike intervals	Time-stamp sequence
OTFS received waveform	ZAK-sampled delay–Doppler coefficients	DD-domain samples

This range of examples shows that TDDC is not restricted to a single hardware primitive. In one class, the time variable already exists physically and must be measured with high precision, as in TDCs for leading-edge timing. In another, the system deliberately creates a time proxy—pulse width, oscillation period, or discharge duration—because timing can be handled efficiently by digital counters, delay lines, or asynchronous event encoders. A plausible implication is that TDDC is best understood as a design pattern: map the target variable into time, then exploit the regularity of digital timing resources to encode it.

2. Principal architectural forms

Two circuit-level TDC strategies recur in the FPGA literature. The first is delay-line or carry-chain sampling, in which many flip-flops sample a tapped delay chain; the second is multi-phase clock sampling, in which several phase-shifted clocks sample the same edge. The multi-phase formulation makes the nominal bin size explicit as

$\text{bin}=\frac{1}{f\times P},$

with $f$ the sampling clock frequency and $P$ the number of phases. In the Kintex-7 multi-phase design, $f=400\ \text{MHz}$ and $P=4$, giving a base bin of $625\ \text{ps}$ before multi-hit refinement (Dong et al., 2020).

A different TDDC form appears in voltage-to-time ADCs. In the PET-oriented Kintex-7 design, the analog input is compared with a quasi-triangular reference generated from a 25 MHz FPGA clock, an off-chip resistor, and input capacitance; the comparator output pulse width is then measured by a carry-chain TDC. Two interleaved channels shifted by $180^\circ$ yield an effective sampling rate of $t_m$0, so the conversion path is explicitly voltage $t_m$1 pulse width $t_m$2 digital code (Ma et al., 2022).

In sensor interfaces, the mapping can be even simpler. The battery-free resistive sensor discharges the storage capacitor $t_m$3 through the sensor resistance $t_m$4, and the microcontroller measures the discharge time between two voltage thresholds. Under the stated approximation,

$t_m$5

so the digital count $t_m$6 is the digitized time-domain proxy for resistance (Costanza et al., 22 Jul 2025).

Event-driven samplers generalize the same idea. In the integrate-and-fire time-encoding machine, the biased signal is integrated until a threshold is reached: $t_m$7 The digital information is then the set of spike times $t_m$8 or inter-spike intervals $t_m$9, not uniform amplitude samples. This is the basis of asynchronous sub-Nyquist ADCs, compressed IF-TEM architectures, and adaptive compressed variants that integrate compression into a clockless TDC (Naaman et al., 2023, Tarnopolsky et al., 2022, Karp et al., 4 Nov 2025).

3. High-resolution FPGA TDC implementations

The Kintex-7 multi-phase TDC of 2020 addressed the classic limitation of multi-phase sampling—coarse base bins—by re-measuring the same input edge multiple times. A circular input buffer in the I/O tile, implemented with MUX, IDELAY, and inverter feedback, launches a controlled local oscillation. An ISERDES core in oversample mode samples the delayed input with four 400 MHz quadrature clocks, while a pipelined encoder converts the resulting thermometer-like code into fine-time words. With $N_m$0 oscillation cycles, the effective bin size is reduced from $N_m$1 to $N_m$2, the measured dual-channel time resolution is better than $N_m$3, DNL is $N_m$4 to $N_m$5, INL is $N_m$6 to $N_m$7, and dead time is below $N_m$8 (Dong et al., 2020).

Carry-chain TDCs pursue finer intrinsic interpolation. The 64-channel Kintex-7 design based on tapped-delay lines and four-edge Wave Union A used 400-tap TDLs, 400 MHz sampling, and a de-bubbling pipeline that explicitly handled severe bubble errors caused by clock-region skew. It reported an average LSB at the $N_m$9 level, an overall average RMS precision of $\text{bin}=\frac{1}{f\times P},$0, and a maximum RMS below $\text{bin}=\frac{1}{f\times P},$1 across 32 rising-edge and 32 falling-edge channels. The same work stressed that large INL can be removed by bin-by-bin calibration, whereas timing precision is mainly limited by DNL and jitter (Liang et al., 2024).

The UltraScale+ design based on four-edge Wave Union A, dual-sampling, sub-TDL decomposition, and a bidirectional encoder pushed the nominal resolution further. Using a 450 MHz sampling clock, CARRY8 dual-sampling, and sub-TDL decomposition to suppress bubbles, it achieved an LSB of about $\text{bin}=\frac{1}{f\times P},$2–$\text{bin}=\frac{1}{f\times P},$3 and a best-case RMS precision of $\text{bin}=\frac{1}{f\times P},$4. The same measurements also showed that RMS over a $\text{bin}=\frac{1}{f\times P},$5–$\text{bin}=\frac{1}{f\times P},$6 interval sweep fluctuated roughly between $\text{bin}=\frac{1}{f\times P},$7 and $\text{bin}=\frac{1}{f\times P},$8, indicating that once the interpolator resolution reaches the sub-picosecond regime, coarse-clock jitter becomes the dominant system term (Wang et al., 2022).

A distinct line of improvement appeared in the Virtex-7 cross-detection and dual-side-monitoring scheme. Cross-detection reordered the sampled CARRY4 outputs to align the code with actual temporal ordering, reducing bubble occurrence from the conventional thermometer pattern, while dual-side monitoring used both start-of-propagation and end-of-propagation information, with only one additional CARRY4, to compensate jitter and PVT-induced drift. The resulting CD-DSM TDC reported an average bin size of $\text{bin}=\frac{1}{f\times P},$9, RMS of $f$0, DNL of $f$1, INL of $f$2, and a $f$3 coincidence timing resolution when measuring two CRI-MCP-PMTs, essentially matching a high-end oscilloscope (Lee et al., 2024).

Taken together, these implementations show three distinct routes to high-resolution FPGA TDDC: repeated measurement on a stable multi-phase clocking fabric, aggressive carry-chain interpolation with Wave Union and bubble-aware encoding, and architecture-level compensation of sampling-path asymmetries. This suggests that “resolution” in FPGA TDDC is a joint outcome of interpolation method, encoding robustness, clock quality, and calibration policy rather than of raw tap delay alone.

4. Time-based ADCs and asynchronous time encoders

The PET-oriented FPGA-ADC demonstrates a classical voltage-to-time TDDC architecture. Two 25 MHz clocks with $f$4 phase shift are shaped by $f$5–$f$6 networks into quasi-triangular ramps, each compared with the analog input by an LVDS receiver. The resulting pulse widths are measured by two calibrated carry-chain TDCs and digitally corrected for nonlinearity, gain, and offset. The design achieved $f$7, ENOB of about $f$8 bits at $f$9, about $P$0 bits at $P$1, INL within $P$2 without any correction over a $P$3 to $P$4 input range with $P$5 offset, and about $P$6 energy resolution at $P$7 in a $P$8 PET measurement (Ma et al., 2022).

The hardware prototype of a time-encoding sub-Nyquist ADC moves to asynchronous conversion. It uses an integrate-and-fire time-encoding machine, a compactly supported sum-of-sincs kernel, and digital recovery of finite-rate-of-innovation parameters from spike times. The prototype operated at firing rates around $P$9–$f=400\ \text{MHz}$0, approximately $f=400\ \text{MHz}$1 times below the Nyquist rate for the tested signals, and achieved delay-estimation errors down to about $f=400\ \text{MHz}$2. A partial-sum formulation replaced a less stable forward model, yielding up to $f=400\ \text{MHz}$3 improvement in delay MSE under realistic timing jitter (Naaman et al., 2023).

Compressed IF-TEM extended this line by performing analog compression in the time domain before quantization. The dynamic range of inter-spike intervals is partitioned into windows, and the sample is represented by a window index plus a local offset. With the same number of samples and up to $f=400\ \text{MHz}$4 additional bits, it improved MSE by $f=400\ \text{MHz}$5–$f=400\ \text{MHz}$6 relative to conventional IF-TEM; for fixed MSE and sample count, it enabled the use of $f=400\ \text{MHz}$7–$f=400\ \text{MHz}$8 fewer bits (Tarnopolsky et al., 2022). Adaptive Compressed IF-TEM then combined adaptive biasing and compressed time encoding in a clockless TDC architecture, reporting at least a $f=400\ \text{MHz}$9-bit gain out of $P=4$0 bits over AIF-TEM and $P=4$1 compression over IF-TEM for fixed recovery MSE with real audio signals (Karp et al., 4 Nov 2025).

Modulo event-driven sampling addressed the dynamic-range failure mode of asynchronous sigma–delta time encoders. By placing a modulo-hysteresis nonlinearity before the ASDM, it forced the encoded waveform into the admissible range of the event-driven front-end and then digitally unfolded the folds from the event-time sequence. In a synthetic example where standalone ASDM produced only 14 spikes and a reconstruction error of $P=4$2, MEDS produced 220 spikes and about $P=4$3 reconstruction error; hardware validation on a sinusoid yielded about $P=4$4 error (Florescu et al., 2022).

These examples locate TDDC within the broader transition from amplitude-domain quantization to time encoding. They also delimit the regime in which such claims hold. Sub-Nyquist operation in the IF-TEM prototype is tied to an FRI model; exact recovery conditions in compressed and adaptive IF-TEM rely on bandlimitedness and spike-density constraints; unlimited-sampling arguments in MEDS rely on modulo-hysteresis and explicit reconstruction inequalities. The time-domain representation is therefore not intrinsically model-free.

5. Sensor interfaces and energy-autonomous TDDC

The energy-autonomous wireless sensing node of 2025 is a notably “pure” TDDC implementation because it reuses the system storage capacitor as the sensing capacitor. The photovoltaic energy-harvesting unit charges $P=4$5 to $P=4$6; during measurement, the unknown resistor $P=4$7 is connected so that it discharges $P=4$8 down to $P=4$9. A programmable voltage detector acts as comparator, and the STM32 low-power timer running at $625\ \text{ps}$0 counts the discharge duration. With $625\ \text{ps}$1, $625\ \text{ps}$2, $625\ \text{ps}$3, and $625\ \text{ps}$4 at 1900 lux, a $625\ \text{ps}$5 test resistance gave $625\ \text{ps}$6 and $625\ \text{ps}$7 counts (Costanza et al., 22 Jul 2025).

The transfer law is linear in the ideal model,

$625\ \text{ps}$8

and the paper explicitly reports a linear relationship between $625\ \text{ps}$9 and $180^\circ$0 within the operating range. It also makes the measurement-energy budget explicit: $180^\circ$1 which is independent of $180^\circ$2. This is a distinctive system-level property of the chosen TDDC mapping: the sensing energy cost is fixed by capacitor and threshold design, not by the sensor value itself (Costanza et al., 22 Jul 2025).

The measurements further show the difference between linearity and absolute accuracy. Using nominal component values in the ideal model gave $180^\circ$3 and relative errors within roughly $180^\circ$4. Using a calibrated linear fit improved the coefficient of determination to $180^\circ$5 and reduced relative errors to about $180^\circ$6. The paper attributes the gain error to about $180^\circ$7 uncertainty in $180^\circ$8, nonzero GPIO output resistance, and uncertainty in $180^\circ$9 and $t_m$00 (Costanza et al., 22 Jul 2025).

The same timer and comparator are also reused for harvested-power estimation, and the entire measurement is carried out with the MCU in stop mode at about $t_m$01, or $t_m$02. This suggests a system architecture in which TDDC is not an isolated converter block but a unifying time-domain substrate for sensing, power management, and communication scheduling.

6. Direct time-domain to delay–Doppler conversion

In OTFS, “time-domain to digital conversion” appears in a different but technically consistent sense: the receiver converts a continuous-time received waveform into a discrete delay–Doppler array. The conventional receiver first applies OFDM demodulation to obtain a time–frequency representation and then applies an SFFT to reach the delay–Doppler domain. The alternate receiver proposed for very high mobility bypasses the intermediate TF grid and converts the received signal directly to DD coordinates by means of the ZAK transform (Mohammed, 2020).

The direct receiver samples the ZAK transform on the delay–Doppler grid and obtains

$t_m$03

so for each delay index $t_m$04, the DD-domain coefficients are obtained by an $t_m$05-point DFT across time samples taken at offset $t_m$06. This architecture removes the OFDM demodulator and yields lower complexity than the two-step conversion (Mohammed, 2020).

The distinction matters in very high mobility. The paper shows that the DD-domain signal produced by direct TD$t_m$07DD conversion is not the same as the DD-domain signal produced by TD$t_m$08TF$t_m$09DD conversion. In a single-path example, the spectral efficiency of the direct ZAK receiver becomes $t_m$10, invariant to Doppler shift, whereas the two-step receiver yields

$t_m$11

which degrades linearly with normalized Doppler. In the UAS CNPC scenario studied in the paper, the direct receiver preserved SE across large speeds, and at $t_m$12 and $t_m$13 gave about $t_m$14 higher SE than the two-step receiver (Mohammed, 2020).

This communication-theoretic usage broadens the notion of TDDC. Here the “digital code” is not a scalar timing word but a structured DD-domain array, and the conversion objective is not merely precise timestamping but preservation of channel sparsity and spectral efficiency under large Doppler.

7. Metrics, calibration, and recurrent trade-offs

Across these architectures, the recurrent performance descriptors are bin size or LSB, DNL, INL, RMS timing precision, dead time, dynamic range, ENOB, coefficient of determination, and reconstruction MSE. The same papers also show that these metrics do not collapse to a single notion of “resolution.” The UltraScale+ Wave Union TDC reports an LSB of about $t_m$15–$t_m$16, yet best-case RMS is $t_m$17 and degrades to roughly $t_m$18–$t_m$19 when coarse-clock involvement increases; the 64-channel Kintex-7 TDC reports $t_m$20-level average LSB but $t_m$21 average RMS precision (Wang et al., 2022, Liang et al., 2024). Fine nominal quantization therefore does not by itself determine end-to-end precision.

Calibration policy is another axis of divergence. Carry-chain and Wave Union TDCs typically rely on code-density calibration and bin-by-bin LUTs; the 64-channel Kintex-7 design states explicitly that INL is removed by calibration and that DNL and jitter then dominate residual precision (Liang et al., 2024). The PET FPGA-ADC likewise uses online delay-tap calibration and a large LUT to linearize the voltage-to-time transfer (Ma et al., 2022). By contrast, the multi-phase ISERDES design obtained DNL and INL within about $t_m$22 without explicit nonlinearity correction, and the high-speed-transceiver DTC achieved $t_m$23 resolution, $t_m$24 to $t_m$25 dynamic range, DNL of $t_m$26, and INL of $t_m$27 without calibration because timing is set by the stability of the transceiver clock rather than by analog delay matching (Dong et al., 2020, Kong et al., 2024).

Sensor TDDC adds a different caution. The battery-free resistive sensor shows that an intrinsically linear time-domain mapping can still suffer large uncalibrated gain error from capacitor tolerance, GPIO resistance, and threshold uncertainty (Costanza et al., 22 Jul 2025). Conversely, event-driven samplers show that low sampling rate or compression gains are meaningful only under explicit structural assumptions: FRI in the sub-Nyquist IF-TEM ADC, bandlimitedness and stationarity in compressed IF-TEM, adaptive bias validity in ACIF-TEM, and modulo-hysteresis plus separation conditions in MEDS (Naaman et al., 2023, Tarnopolsky et al., 2022, Karp et al., 4 Nov 2025, Florescu et al., 2022).

The technical record therefore presents TDDC as a heterogeneous but coherent field. Its common principle is the same—encode information in time, then digitize that timing structure—but its concrete realizations range from picosecond FPGA interpolators to RC discharge sensors, asynchronous samplers, and delay–Doppler receivers. The main design question is not whether a system is “time-based,” but which temporal representation is most stable, most calibratable, and most informative for the target application.