Tapped-Delay Lines Fundamentals

• Tapped-delay lines are chains of discrete delay elements that sample input signals at quantized intervals to capture fine-grained temporal information.
• They are applied in diverse areas such as time-to-digital converters, wideband channel modeling, optical signal processing, and computational memory systems.
• Recent innovations include multi-chain averaging and iterative time-bin interleaving, which enhance resolution, precision, and resource efficiency in modern implementations.

A tapped-delay line (DL) is a one-dimensional chain or network of discrete delay elements or “taps,” each introducing a fixed propagation delay to a signal. The outputs from these taps represent the state of the propagating waveform at distinct, quantized time intervals or spatial positions. Tapped-delay lines constitute foundational structures with applications in time-to-digital conversion, channel modeling, memory architectures, signal processing, and computational models for memory in neural systems. Their essential utility derives from their ability to encode signal history or temporal structure into an array of parallel outputs, which may then be analyzed or processed by downstream systems or readouts.

1. Formal Definitions and Theoretical Foundations

The canonical tapped-delay line consists of $N$ identical delay cells, each inserting a delay $t_{\text{cell}}$. The aggregate delay from the input to the $k$th tap is $t_{\text{total}}(k) = k \cdot t_{\text{cell}}$. The general architecture can be depicted as:

In ─▶│ D │─▶│ D │─▶│ D │─▶ ... ─▶│ D │ │ │ │ │ Tap₁ Tap₂ Tap₃ Tapₙ

At each tap, the arrival of the input signal is sampled, yielding a digitized representation of the fine time or signal profile relative to a reference (e.g., the system clock in TDCs) (Shen et al., 2014).

Mathematically, the state update for a discrete-time delay line with input $u(t)$ and state vector $X(t) \in \mathbb{R}^N$ is

$$X_1(t) = u(t), \quad X_j(t+1) = X_{j-1}(t)\,,\quad (j > 1)$$

or in matrix form,

$X(t+1) = A X(t) + b u(t)$

where $A$ is the $N \times N$ shift matrix and $b$ the input selector (Goudarzi et al., 2014).

In wideband multipath channel modeling, the TDL expresses the baseband impulse response as

$$h(t, \tau) = \sum_{n=0}^{N-1} a_n(t) e^{j\phi_n(t)} \delta(\tau - \tau_n),$$

where each tap represents a resolvable multipath component arriving at relative delay $\tau_n$ with complex amplitude $a_n(t) e^{j\phi_n(t)}$ (Zhang et al., 27 Jan 2025).

2. Realizations in Time-to-Digital Converters and Digital Logic

Tapped-delay lines serve as the core of fine-time measurement in FPGA-based TDCs. An input transition propagates through a chain of delay cells (usually composed of carry-chain primitives such as CARRY4 or CARRY8 in Xilinx FPGAs), with synchronous sampling at each tap yielding a "thermometer code"—a contiguous run of 1's followed by 0's, indicating propagation depth at the clocking instant (Shen et al., 2014, Park et al., 5 Nov 2025, Dong et al., 2022).

Key parameters:

• Resolution ($\Delta t$): Equal to the cell delay, typically 3–25 ps depending on fabrication node and design.
• Precision ($\sigma$): RMS error set by manufacturing dispersions, $1/\sqrt{M}$ scaling via multi-chain averaging.
• Dynamic Range: Set by $N \Delta t$, extended via a coarse counter.
• Nonlinearity: Characterized by DNL and INL metrics; reduced via calibration and averaging/interleaving (Park et al., 5 Nov 2025).

Recent architectural advances:

• Multi-chain averaging: $M$ parallel TDLs with staggered inputs, outputs averaged, yielding $1/M$ bin-size scaling and improved precision as $1/\sqrt{M}$ (Shen et al., 2014).
• Iterative time-bin interleaving (ITI): Calibrated bins from multiple chains merged into a larger, unified TDL without explicit averaging, achieving picosecond resolution and sub-LSB DNL/INL (Park et al., 5 Nov 2025).
• Resource-efficient encoding: Divide-and-conquer thermometer-to-binary encoding architectures drastically reduce FPGA LUT/register resources and dead time (Dong et al., 2022).

Architecture	Resolution (ps)	Precision (ps)	Hardware Overhead
Single-chain TDL	24	18	Baseline
8-chain Averaged	3	6.5	8× TDL, calibration
POR/ITI Interleaved	1.15	3.38	Minimal, post-proc.

3. Tapped-Delay Lines in Channel Modeling

TDL models are the standard paradigm for simulating the impulse response of wideband multipath wireless channels. Each tap corresponds to a distinct propagation path characterized by relative delay, time-varying amplitude, random phase, Doppler shift, and statistical birth/death modeled as Markov processes for nonstationary channels (Zhang et al., 27 Jan 2025). For example, a 5-tap model for 5G railway channels uses log-normal amplitude distributions, uniform phase/Doppler, and fitted Markov cross-switches with empirically estimated transition matrices.

Key properties for rigorous modeling:

• Number of taps ($N$): Defined by the resolvability of multipath structure in temporal domain.
• Delay set $\{\tau_n\}$: Determines channel delay spread and ISI.
• Statistical models: Amplitude (log-normal), phase (uniform), Doppler (uniform), state transitions (first-order Markov).
• Inter-tap correlation: Non-negligible in realistic scenarios, enforced via multivariate log-normal draws.
• Validation: Comparison to measurement data and established models (e.g., 3GPP TR 38.901).

Tap $\#\ n$	Delay ($\mu$s)	Mean Power (dB)	Steady-State Probability
1	0.0	0.00	1.00
2	0.1	-3.14	0.77
3	0.2	-17.02	0.55
4	0.3	-26.31	0.42
5	0.4	-39.35	0.46

4. Tapped-Delay Memory Architectures in Hardware

Tapped-delay lines underpin memory constructs in both semiconductor and superconductor domains. Superconductor-based delay-line memories utilize passive transmission lines formed from Nb or MoN/NbTiN to achieve low-attenuation, high-speed delay loops. Read/write taps are implemented using SFQ (single flux quantum) gating cells, enabling sequential and content-addressable memory operation at 20–100 GHz clock rates and data densities up to 10–100 Mbit/cm$^2$ (Volk et al., 2022). The tap density and addressability are determined by the physical delay per unit length, fabrication process minimums, and the propagation velocity $v_p = 1/\sqrt{L'C'}$.

5. Optical and Photonic Tapped-Delay Lines

Tapped-delay lines are realized in photonics and all-optical networking as sampled true-time-delay lines (TTDLs), particularly using trench-assisted heterogeneous multicore fibers (TA-MCF) (Garcia et al., 2018). Each core in the MCF acts as a tap, introducing a distinct group delay and enabling FIR filtering, microwave signal processing, and beamforming in fiber-wireless communication systems.

Design principles:

• Tap spacing ($\Delta\tau$): Engineered via dispersion differences among cores, tunable by optical wavelength.
• Crosstalk/Bend Sensitivity: Suppressed via index-mismatched core design; $<$–90 dB crosstalk over 10 km.
• Filter response: $H(\omega)=\sum_n a_n e^{-j\omega\tau_n}$ implements the desired delay-sampled FIR filter.
• Dynamic reconfiguration: Achieved by controlling optical source wavelength, modifying free-spectral-range (FSR).

6. Tapped-Delay Lines in Computational Models

In computational neuroscience and machine learning, the tapped-delay line provides a pure memory structure—carrying no internal nonlinearity but enabling perfect input history storage for $N$ time steps (Goudarzi et al., 2014). When combined with a linear readout (regression), this forms a baseline against which the capacity and generalization of more nonlinear dynamical systems (like echo-state networks or NARX networks) are measured.

Findings:

• Memory capacity: Exact for delay lines; a DL with $N$ taps stores the past $N$ values with zero information loss, but lacks the expressive power for generalization on nonlinear prediction tasks.
• Overfitting: Excessive $N$ leads to extremely poor generalization as the system merely memorizes rather than infers underlying dynamics.
• Comparison: Reservoirs (ESNs) deliver orders-of-magnitude better test error on nonlinear mappings for the same parameter count.

System	Training RNMSE (NARMA10)	Test RNMSE (NARMA10)
DL (N=10)	0.0001	1.16
ESN (N=100)	<0.33	<0.33

7. Advanced and Specialized Architectures

Tapped-delay lines form the backbone of scalable optical priority queues and optical buffer architectures. In optical switches with $(M+2)\times(M+2)$ crossbars and $M$ fiber-delay lines (SDL), each FDL can be equipped with multiplexed "tap groups" (FIFO multiplexers), supporting sophisticated packet routing and subexponential buffer depth ($B^* = 2^{\Theta(\sqrt{M})}$) (Tang et al., 2019). The logical depth achievable in such feedback and multiplexed SDL architectures approaches that of ideal exponential buffers while using only polynomial hardware resources.

• "A Multi-chain Measurements Averaging TDC Implemented in a 40 nm FPGA" (Shen et al., 2014)
• "Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration" (Park et al., 5 Nov 2025)
• "A low dead time, resource efficient encoding method for FPGA based high-resolution TDL TDCs" (Dong et al., 2022)
• "Measurement-Based Non-Stationary Markov Tapped Delay Line Channel Model for 5G-Railways" (Zhang et al., 27 Jan 2025)
• "Addressable Superconductor Integrated Circuit Memory from Delay Lines" (Volk et al., 2022)
• "RF photonic delay lines using space-division multiplexing" (Garcia et al., 2018)
• "A Comparative Study of Reservoir Computing for Temporal Signal Processing" (Goudarzi et al., 2014)
• "Construction of Subexponential-Size Optical Priority Queues with Switches and Fiber Delay Lines" (Tang et al., 2019)