Adiabatic Capacitive Neuron Architecture

• Adiabatic Capacitive Neuron (ACN) is a mixed-signal, switched-capacitor artificial neuron that uses adiabatic power-clock operation to perform binary threshold computations.
• It implements the weighted summation through a differential dual-tree architecture, converting ANN parameters to physical capacitances while ensuring robust charge recovery.
• ACN designs prioritize energy efficiency and practical hardware trade-offs, making them ideal for chip-scale neural networks in energy-sensitive edge computing applications.

Searching arXiv for recent ACN-related papers and closely related prior work. Searching arXiv for “Adiabatic Capacitive Neuron” and “Adiabatic Capacitive Neural Network”. An Adiabatic Capacitive Neuron (ACN) is a mixed-signal, switched-capacitor artificial neuron that implements the standard binary-threshold artificial-neuron computation through charge redistribution and adiabatic power-clock operation rather than resistive or purely digital arithmetic. In the ACN literature, the neuron preserves the usual ANN workflow—weighted summation followed by a thresholded output—but realizes the weighted sum as a capacitive dot product and recovers charge during the falling phase of a sinusoidal or quasi-sinusoidal power clock. The term is used most specifically for the dual-tree single-clock (DTSC) architecture introduced as a practical hardware replacement for a conventional artificial neuron, and for the larger Adiabatic Capacitive Neural Network (ACNN) chips constructed from such neurons (Maheshwari et al., 1 Jul 2025, Raghav et al., 16 Dec 2025).

1. Definition and conceptual position

In software form, the target computation is the binary-threshold neuron

$$y = \begin{cases} 1, & \text{if } \sum_{i \in I} w_i x_i \ge \tau \ 0, & \text{otherwise} \end{cases}$$

with binary inputs $x_i$, signed weights $w_i$, and threshold $\tau$. ACN hardware maps this decision rule into a comparison of two membrane voltages generated by capacitive charge division in a positive tree and a negative tree (Maheshwari et al., 1 Jul 2025, Smart et al., 15 Sep 2025).

The ACN emerged as a development beyond the earlier Adiabatic Capacitive Artificial Neuron (ACAN). ACAN already combined an adiabatic capacitive synaptic tree with a dynamic latched comparator, but the later ACN introduced support for both positive and negative weights, a differential architecture less sensitive to power-clock variation, and a revised threshold-logic stage with lower offset (Maheshwari et al., 2022, Maheshwari et al., 1 Jul 2025). In this lineage, ACAN is best understood as a precursor architecture, whereas ACN denotes the differential dual-tree formulation that became the basis for the 2025 chip-scale ACNN implementation (Raghav et al., 16 Dec 2025).

A common misconception is to equate ACN with any neuron model involving capacitance. The term in this hardware context refers to an artificial neuron whose computation is intentionally organized around adiabatic charge recovery, switched-capacitor weighted summation, and thresholded digital output. This differs from biophysical models in which time-dependent membrane capacitance modifies excitability in a FitzHugh–Nagumo system, and it also differs from electromechanical memcapacitive spiking devices whose dynamics arise from movable-plate capacitance and state-dependent leakage rather than from adiabatic ANN inference hardware (Courdurier et al., 29 Jan 2025, Zhang et al., 2023).

2. Circuit organization and operating principle

The canonical ACN is the DTSC architecture. It contains two switched-capacitor arrays, one for positive weights and one for negative weights, both driven by a single sinusoidal power clock. Each input bit controls a single-pole double-throw switch: when $x_i=1$, the corresponding synapse capacitor is connected to the adiabatic power clock; when $x_i=0$, it is connected to ground. Each tree also contains a bias capacitor $C_b^\pm$, a ballast capacitor $C_d^\pm$, and DC bias rails $V_B^\pm$, producing membrane voltages $v_m^+(t)$ and $x_i$0 (Maheshwari et al., 1 Jul 2025, Smart et al., 15 Sep 2025).

The membrane voltages are expressed as

$x_i$1

and, in the more explicit form used for the 12-bit neuron,

$x_i$2

The threshold logic samples the membrane voltages near the peak of the power clock and outputs a binary decision: $x_i$3 if $x_i$4, otherwise $x_i$5 (Maheshwari et al., 1 Jul 2025, Smart et al., 15 Sep 2025).

This operating principle makes the “multiply” and “accumulate” stages physical rather than symbolic. Weighting is implemented by capacitor selection and capacitor sizing, and accumulation is implemented by charge sharing on the membrane nodes. In the ACNN chip, each ACN performs a capacitive multiply-accumulate operation in one adiabatic power-clock cycle, and the chip is described as containing 16 mixed-signal processors capable of single-cycle MAC computations at 1 MHz (Raghav et al., 16 Dec 2025).

A central architectural property of DTSC ACN is differential common-mode rejection of power-clock variation. Because both trees are driven by the same power-clock structure, the binary decision can be made independently of the exact power-clock amplitude under the balanced comparison formulation. The literature presents this as a robustness advantage over earlier single-ended styles that depended on absolute reference voltages (Smart et al., 15 Sep 2025, Maheshwari et al., 1 Jul 2025).

3. Weight mapping from ANN parameters to physical capacitances

ACN implementation depends on a weight-to-capacitance mapping that preserves the neuron’s binary decision boundary under realizable capacitor constraints. The mapping problem is treated explicitly in the DTSC analysis paper, which shows that a naïve proportional mapping is insufficient because the relevant invariant is the sign of the dot-product decision, not the exact numerical value of $x_i$6 (Smart et al., 15 Sep 2025).

The basic proportionality is written as

$x_i$7

leading under the balanced-tree condition to

$x_i$8

with

$x_i$9

In the 2025 ACNN chip paper, the trained network weights are quantized to 8 bits in the range $w_i$0 with a dead zone around zero and then mapped to physical capacitance values using an “optimal conditional mapping” method. The minimum capacitance is set to $w_i$1, the power-clock peak voltage is $w_i$2, and the total synapse capacitance per neuron is given by

$w_i$3

That mapping is described as theoretically exact, with small silicon deviations arising from capacitor quantization and parasitic-to-ground capacitances on the membrane nodes (Raghav et al., 16 Dec 2025).

The mapping is termed conditional because ballast placement depends on whether the positive or negative total weight magnitude is larger. For $w_i$4, one form is

$w_i$5

with the simpler bias case

$w_i$6

for $w_i$7, and a symmetric expression for $w_i$8. The stated optimization objectives are exact functional equivalence between ANN and ACN binary outputs, minimal total ballast capacitance, and maximal differential membrane voltage $w_i$9, since larger $\tau$0 improves comparator robustness (Smart et al., 15 Sep 2025).

The same literature emphasizes that capacitor realizability strongly shapes the mapping. Minimum manufacturable capacitance $\tau$1, capacitor quantization, and parasitic loading constrain the translation from trained weights to hardware. In the ACNN chip, unit MOM capacitors are about $\tau$2 each, the average post-layout capacitance error is reported as $\tau$3, and the resulting predicted classification loss is only $\tau$4. About $\tau$5 of the required ballast capacitance is obtained from parasitics, which are thus partly used as an asset rather than treated purely as error sources (Raghav et al., 16 Dec 2025).

4. Adiabatic energy recovery and threshold logic

The distinctive feature of ACN is not merely capacitive computation but adiabatic capacitive computation. In a conventional switched-capacitor RC load, charging from a DC source dissipates $\tau$6 and discharging to ground dissipates another $\tau$7, for a total of $\tau$8. In the adiabatic case, a sinusoidal or quasi-sinusoidal power clock charges the load gradually during evaluation and recovers charge during the recovery phase, returning much of the stored energy to the supply rather than dumping it to ground (Raghav et al., 16 Dec 2025).

For the 12-bit ACN, the adiabatic synapse loss is written as

$\tau$9

and the total energy per cycle as

$x_i=1$0

with

$x_i=1$1

The earlier ACAN work used an LC resonant power-clock generator with evaluation, recovery, and reset/top-up phases, and emphasized the standard adiabatic design rules: open a switch only when there is no voltage across it, and close a switch only when no current flows through it (Maheshwari et al., 1 Jul 2025, Maheshwari et al., 2022).

Threshold detection in ACN is deliberately non-adiabatic but high impedance. In the single-neuron ACN, the threshold logic is a two-stage pMOS-based circuit consisting of a dynamic latch clocked comparator followed by a clocked set-reset latch. The design goal is a binary activation block with low and symmetrical offset so that small differential membrane voltages can still be resolved without materially disturbing the adiabatic charge-recovery process of the synaptic trees (Maheshwari et al., 1 Jul 2025, Raghav et al., 16 Dec 2025).

Across three process corners and five temperatures from $x_i=1$2 to $x_i=1$3, the proposed threshold logic shows rising and falling offsets of about $x_i=1$4 to $x_i=1$5 and $x_i=1$6 to $x_i=1$7, respectively, whereas the conventional comparator used for reference exhibits larger asymmetry. The proposed design also shows a decrease in average energy of $x_i=1$8 at the SS corner and $x_i=1$9 at the FF corner compared to the conventional threshold logic (Maheshwari et al., 1 Jul 2025).

5. Implementations and measured performance

The first detailed DTSC ACN implementation reported in 2025 is a 12-bit single neuron in $x_i=0$0 CMOS at $x_i=0$1. Its layout dimensions are $x_i=0$2, the nominal power-clock frequency is $x_i=0$3, and the reported synapse energy savings relative to a non-adiabatic CMOS capacitive neuron benchmark are above $x_i=0$4, with some vectors reaching about $x_i=0$5 savings. The post-layout neuron correctly produces logic 1 for $x_i=0$6, whereas the conventional threshold-logic ACN requires approximately $x_i=0$7 to $x_i=0$8 (Maheshwari et al., 1 Jul 2025).

The chip-scale realization is the dual-layer ACNN image-classification processor fabricated in 130 nm CMOS. It contains 16 ACNs total—12 neurons in the first layer and 4 in the second layer—implementing a software-trained two-layer ANN with 64 binary inputs, 12 hidden neurons, and 4 outputs. The 64-bit image is loaded serially via SPI into a deserializer, applied in parallel to the first layer, passed through a routing layer, and produces a final 4-bit output $x_i=0$9; the 12 first-layer outputs $C_b^\pm$0 are also externally accessible for debugging. The chip area is $C_b^\pm$1, with the ACNs and routing layer occupying an internal core of $C_b^\pm$2 (Raghav et al., 16 Dec 2025).

The routing layer is architecturally important because it decouples the two computational layers and handles timing and synchronization. It consists of an adiabatic buffer, a dynamic latch clocked comparator, and a clocked SR latch, and is driven by a second power clock $C_b^\pm$3 phase-shifted by $C_b^\pm$4 relative to $C_b^\pm$5. The resulting design therefore uses two coordinated adiabatic clock domains, one for the ACN layers and one for routing and hand-off between layers (Raghav et al., 16 Dec 2025).

On the arrows8 image-classification task, the software ANN achieves $C_b^\pm$6 accuracy on the 4,078-sample dataset, while the ACNN hardware achieves over $C_b^\pm$7 classification, within $C_b^\pm$8 of the software version overall. Across five chips and repeated runs, hardware/software mismatch is typically $C_b^\pm$9 to $C_d^\pm$0, with standard deviation below $C_d^\pm$1 across repeated measurements on each chip. The remaining errors are strongly associated with small differential membrane voltages: $C_d^\pm$2 of the bit-error samples are predicted to have $C_d^\pm$3, while layer 2 is described as more robust because its predicted differential voltages are usually above $C_d^\pm$4 (Raghav et al., 16 Dec 2025).

Energy efficiency is a principal result. Compared with an equivalent DC-powered CMOS capacitive neural network, the ACNN shows an average $C_d^\pm$5 reduction in measured energy dissipation at 30 operations, while the post-layout model predicts about $C_d^\pm$6 improvement. At 500 operations, with decaying tank amplitude when the tank capacitor is not recharged between operations, the measured average reduction reaches $C_d^\pm$7. The comparison table further reports an energy metric of $C_d^\pm$8 per synapse operation at 1 MHz, using Chip2’s $C_d^\pm$9 excluding threshold-logic energy at 500 operations for comparison (Raghav et al., 16 Dec 2025).

6. Design trade-offs, robustness, and relation to adjacent research

ACN design is intentionally inference-oriented. The hardware chip is hard-coded rather than reconfigurable, and the papers present this as a deliberate trade-off that removes configuration overheads and prioritizes energy efficiency over on-chip learning and general reconfigurability. This makes the architecture especially suited to pretrained models, front-end feature extraction, and edge tasks in battery-powered systems where minimizing energy per operation is more important than supporting full retraining (Raghav et al., 16 Dec 2025).

Weight quantization is not treated only as a loss mechanism. In the DTSC mapping study, quantization is reported to improve physical implementability by eliminating tiny weights that would otherwise map to unrealistically small capacitors, reducing required total capacitance, making arrays more regular, and often improving comparator robustness. The paper introduces the instability metric $V_B^\pm$0, defined as the fraction of input samples for which $V_B^\pm$1 lies below a voltage tolerance; in the experiments, a tolerance of $V_B^\pm$2 is used. For binarized MNIST hidden layers mapped into ACN form, quantized and binary networks show lower instability and preserved hidden-layer classification accuracy, with software and hardware both at $V_B^\pm$3 for the 4-bit quantized case and $V_B^\pm$4 for the binary case (Smart et al., 15 Sep 2025).

The limitations are equally clear. ACN requires a specialized resonant power-clock generator; energy optimality depends on frequency and loading; comparator and routing overheads remain non-negligible; and accuracy degrades near the decision boundary where $V_B^\pm$5 is small. The 12-bit single-neuron paper also notes that excluding the CMOS inverter in the SPDT path from synapse energy accounting is favorable to the reported numbers and that including it would increase total synapse energy by about $V_B^\pm$6 to $V_B^\pm$7, although the authors argue that in multilayer networks complementary signals from previous threshold-logic stages can be reused (Maheshwari et al., 1 Jul 2025).

Historically, ACN should be distinguished from two adjacent but non-equivalent lines of research. First, ACAN uses adiabatic capacitive synapses and an RRAM-tuned dynamic comparator, but it lacks the later ACN’s dual-tree positive/negative weight support and common-mode rejection of power-clock variation; its reported proof-of-concept shows $V_B^\pm$8 synaptic energy saving and $V_B^\pm$9 overall energy reduction at 4 synapses per soma (Maheshwari et al., 2022). Second, biophysical and memcapacitive neuron studies establish broader capacitive-neuron concepts without implementing the DTSC ACN architecture. Time-dependent membrane-capacitance models show that abrupt changes in $v_m^+(t)$0 can trigger or suppress action potentials through the charge-balance law $v_m^+(t)$1, while electromechanical leaky memcapacitor neurons use state-dependent capacitance and leakage to generate spiking behavior. These results are conceptually related because they center neural behavior on capacitive state evolution, but they are not ACN implementations in the ANN-hardware sense (Courdurier et al., 29 Jan 2025, Zhang et al., 2023).

Taken together, the ACN literature establishes a specific hardware interpretation of the artificial neuron: a differential, adiabatic, switched-capacitor functional unit in which signed weights are encoded as capacitances, weighted summation is realized by charge redistribution, activation is produced by high-impedance threshold logic, and substantial energy reduction relative to conventional capacitive CMOS is obtained through power-clock-based charge recovery (Maheshwari et al., 1 Jul 2025, Raghav et al., 16 Dec 2025).