SuperSNN: Superconducting SNN Chip Design

• The paper introduces a hardware-aware superconducting SNN framework that co-optimizes off-chip training, pruning, ternary quantization, and custom neuron design to meet chip limitations.
• It demonstrates high performance with 96.47% simulation accuracy on full MNIST and 80–86% on reduced digit sets in a fabricated SFQ chip operating at 3.02 GHz.
• The framework addresses severe physical constraints through innovative input serialization, LAGS clocking, and progressive pruning to achieve efficient energy and speed metrics.

SuperSNN most directly denotes a hardware-aware framework for implementing physically realizable superconducting spiking neural networks and, in the same work, a fabricated Single-Flux-Quantum inference chip in the MIT Lincoln Laboratory SFQ5ee process (Song et al., 5 Sep 2025). The framework co-optimizes off-chip training, pruning, ternary quantization, custom high fan-in neuron cells, and a locally asynchronous, globally synchronous clocking scheme under severe constraints on chip area, routing resources, pin count, and bias/clock distribution. In the reported implementation, the complete network achieved 96.47% accuracy on the full MNIST dataset after quantization and pruning, while the fabricated chip occupied 3.4 × 3.9 mm², incorporated 5,822 Josephson Junctions, operated at 3.02 GHz, and classified the reduced digit set $\{2,3,4\}$ with 80.07% accuracy, reaching 86.2% on $\{0,1,2\}$ (Song et al., 5 Sep 2025).

1. Scope and nomenclature

The label “SuperSNN” is not used uniformly across the literature. In its clearest and most specific sense, it refers to the hardware-aware superconducting SNN framework and chip of “SuperSNN: A Hardware-Aware Framework for Physically Realizable, High-Performance Superconducting Spiking Neural Network Chips” (Song et al., 5 Sep 2025). That usage is distinct from “SupraSNN,” which is a superscalar-inspired FPGA accelerator; the corresponding paper states explicitly that the term “SuperSNN” does not appear there and that “SupraSNN” is the correct name (Ghavami et al., 11 Jun 2026).

Secondary summaries also apply “SuperSNN” to unrelated subjects. An overview of “SuperSpike” uses “SuperSNN” as a shorthand for supervised learning in multilayer spiking neural networks (Zenke et al., 2017), and an overview of self-normalizing neural networks for $b \to c \tau \nu_\tau$ model selection introduces “SuperSNN” as a name for the trained-network bundle (Bhattacharya et al., 2020). These are separate usages rather than a unified technical lineage.

For superconducting neuromorphic hardware, the most coherent usage is therefore the one centered on hardware-aware SFQ SNN realization (Song et al., 5 Sep 2025). A related line of work on superconducting SNN accelerators presents a high-fan-in differential neuron with ternary synaptic connections and reports system-level inference results, but it is not the same named framework (Karamuftuoglu et al., 2024).

Name	Paper	Meaning
SuperSNN	(Song et al., 5 Sep 2025)	Hardware-aware superconducting SNN framework and fabricated chip
SupraSNN	(Ghavami et al., 11 Jun 2026)	Superscalar-inspired FPGA SNN accelerator
“SuperSNN” as shorthand	(Zenke et al., 2017, Bhattacharya et al., 2020)	Secondary naming for unrelated SNN or SNN-like methods

2. Hardware-aware training methodology

SuperSNN uses a simplified leaky integrate-and-fire neuron with hard reset. The spike rule is

$$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$

and the membrane update is

$U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$

with $0 < \beta < 1$ (Song et al., 5 Sep 2025). Training unrolls the computational graph for 25 time steps and uses surrogate gradients for the non-differentiable Heaviside spike function. The surrogate derivative is the arctangent form

$$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$

The baseline objective is a membrane-potential-based loss. At each time step,

$p_i[t] = \frac{e^{U_i[t]}}{\sum_j e^{U_j[t]}},$

with cross-entropy

$L_{\rm CE}[t] = -\sum_i y_i \log p_i[t],$

and total loss

$L_{\rm CE} = \sum_t L_{\rm CE}[t].$

For the chip-constrained network, mem loss alone was reported to under-fit under “single forward pass” and “<25 neurons,” so the framework adds a spike-count loss and uses the hybrid objective

$\{0,1,2\}$0

The input pipeline is explicitly hardware-constrained. The complete network uses binarized $\{0,1,2\}$1 inputs for 25 time steps. The chip network downsamples MNIST from $\{0,1,2\}$2 to $\{0,1,2\}$3 by block averaging with threshold 0.3 and binarization, then executes a single forward pass (Song et al., 5 Sep 2025). This reduction is driven by pin-count and routing limits rather than by algorithmic preference.

Quantization-aware training constrains synaptic weights to ternary values $\{0,1,2\}$4, physically realized by the sign and magnitude of mutual inductive couplings $\{0,1,2\}$5 between a primary inductor and a secondary loop. The pruning schedule is progressive rather than abrupt. If a neuron begins with $\{0,1,2\}$6 connections and targets $\{0,1,2\}$7 after $\{0,1,2\}$8 pruning steps, the fan-in target at step $\{0,1,2\}$9 is

$b \to c \tau \nu_\tau$0

An explicit example prunes the first layer from $b \to c \tau \nu_\tau$1 to $b \to c \tau \nu_\tau$2 over $b \to c \tau \nu_\tau$3 steps (Song et al., 5 Sep 2025).

The chip mapping further regularizes the learned structure. Training reportedly yielded approximately six excitatory and two inhibitory inputs per hidden neuron, and the final hardware standardizes each hidden neuron to exactly six positive and two negative synapses to simplify layout and timing (Song et al., 5 Sep 2025). This suggests that the framework treats network synthesis and physical design as a coupled optimization problem rather than a sequential software-to-hardware compilation pass.

3. Network architecture and superconducting circuit realization

The software-scale network is a five-layer SNN with topology $b \to c \tau \nu_\tau$4, hidden layers $b \to c \tau \nu_\tau$5, and output dimension 10 (Song et al., 5 Sep 2025). Inputs are binarized, weights are ternary, the time window is 25 steps, and classification is performed by output spike count. Fan-in is capped at 64 per neuron. The reported sparsity is substantial: in Hidden Layer 0, of size 100,352, the fractions are 3.94% $b \to c \tau \nu_\tau$6, 3.68% $b \to c \tau \nu_\tau$7, and 92.37% zeros; in the Output Layer, of size 960, the fractions are 7.29% $b \to c \tau \nu_\tau$8, 28.44% $b \to c \tau \nu_\tau$9, and 64.27% zero (Song et al., 5 Sep 2025).

The fabricated chip implements a much smaller three-layer topology. Its input stage contains 49 D flip-flops arranged as a $$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$0 shift-register array. Seven input pins load one row-group per cycle over seven cycles. The hidden layer contains 18 neurons, reduced from 24 after pruning and zero-weight elimination. Each hidden neuron has exactly eight inputs: six positive and two negative. The output layer contains three neurons, and hidden outputs fan out to 23 signals feeding those outputs. Final-layer spikes are converted to DC levels for off-chip readout through three output pins (Song et al., 5 Sep 2025).

Weight realization is magnetic rather than digital-memory based. Each retained synapse is implemented as a mutual inductive coupling branch with coupling coefficient $$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$1 in the provided neuron schematic. Two dendritic bundles are used, labeled BRANCH 1 and BRANCH 2, and the soma fires when

$$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$2

A Josephson Transmission Line is inserted only on the positive path so that inhibitory arrival precedes excitatory arrival, which the paper uses to ensure correct temporal integration (Song et al., 5 Sep 2025).

The custom high fan-in neuron is central to the framework. Selected parameters include $$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$3–$$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$4–$$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$5 pH; $$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$6–$$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$7, $$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$8–$$S[t] = 1 \text{ if } U[t] > U_{\rm thr}, \text{ else } 0,$$9; $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$0, $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$1; branch resistors $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$2; soma inductors $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$3 pH, $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$4 pH, $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$5 pH, $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$6 pH; and critical currents $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$7 mA, $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$8 mA, $U[t+1] = \beta U[t] + W X[t+1] - S[t] U_{\rm thr},$9 mA (Song et al., 5 Sep 2025). Functionally, the neuron combines pulse-to-current integration, resistive leak, excitatory and inhibitory signed accumulation, and hard-reset-like SFQ firing in a single custom cell.

A related superconducting SNN hardware study adopts a different high-fan-in differential neuron composed of multiple superconducting loop branches and two Josephson Junctions, uses ternary weights $0 < \beta < 1$0, and demonstrates a dendrite size of 64 via eight branches, each with four positive and four negative inputs (Karamuftuoglu et al., 2024). That work provides architectural context for the broader design space of superconducting SNNs, but SuperSNN’s distinguishing feature is explicit co-design for a fabricated, pin-limited SFQ5ee chip (Song et al., 5 Sep 2025).

4. Physical constraints, clocking, and on-chip dataflow

The motivating fabrication constraints are severe. The SFQ5ee process limits usable chip area to approximately $0 < \beta < 1$1 mm², provides 40 total pins uniformly distributed around the die, and has a limited number of routing metal layers (Song et al., 5 Sep 2025). The SuperSNN chip itself uses all 40 pins, but after allocating pins for clocks and multiple bias supplies, only 7 pins remain for inputs and 3 for outputs. This is the immediate cause of the $0 < \beta < 1$2 downsampled input representation and serial shift-register loading (Song et al., 5 Sep 2025).

To meet routing and timing constraints, the design uses cascaded splitter trees for fan-out, Passive Transmission Lines for long-distance SFQ propagation, and local D flip-flops for pulse alignment. Maximum fan-out is nine via eight cascaded splitter cells, each contributing 3.1 ps delay, for a total of approximately 24.8 ps. The shift-register front end uses seven data pins and a serial clock, and the total delay across the $0 < \beta < 1$3 shift-register path is 433 ps (Song et al., 5 Sep 2025).

The clocking strategy is described as locally asynchronous, globally synchronous, abbreviated LAGS. Globally, a chip-level clock coordinates shift-register loading, per-layer enable, and output readout. Locally, neuron inputs are retimed via DFFs, so SFQ traffic over PTLs and through splitter trees is not required to remain rigidly phase-aligned to a single global edge at every point on the die (Song et al., 5 Sep 2025). The same source contrasts LAGS with fully asynchronous SFQ and with GALS, arguing that fully asynchronous SFQ is fragile at scale and that GALS requires additional per-island clock domains and more complex clock-domain-crossing logic.

The full inference sequence occupies ten cycles: seven cycles to shift in the $0 < \beta < 1$4 bits, two cycles to propagate inputs through bias enable and inter-layer synchronization, and one cycle to read outputs (Song et al., 5 Sep 2025). The resulting idealized throughput and latency are summarized as

$0 < \beta < 1$5

At $0 < \beta < 1$6 GHz, the idealized inference rate is approximately $0 < \beta < 1$7 inferences/s and the idealized latency is approximately 3.31 ns. Because the serial shift-register path limits throughput to just over 1 GHz, the same analysis notes an effective throughput near $0 < \beta < 1$8 M inferences/s (Song et al., 5 Sep 2025).

Skew and hazard management are handled structurally. DFF retiming at neuron inputs absorbs local skew, splitter and PTL delays are explicitly budgeted, and the excitatory-path JTL creates an inhibitory lead to stabilize the summation order inside the soma (Song et al., 5 Sep 2025). A plausible implication is that, in this regime, timing closure is dominated less by intrinsic JJ switching speed than by interconnect topology, front-end serialization, and synchronization granularity.

5. Reported metrics, energy accounting, and comparison points

The central reported metrics of SuperSNN span both software-constrained and fabricated-hardware regimes (Song et al., 5 Sep 2025).

Metric	Complete network	Fabricated chip
Task	Full MNIST, 10 digits	Reduced digit subsets
Accuracy	96.47%	80.07% on $0 < \beta < 1$9; 86.2% on $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$0
Clock frequency	—	3.02 GHz
Area	—	3.4 × 3.9 mm²
JJ count	—	5,822
Static power	—	2.15 mW

The hardware accuracy depends strongly on the chosen subset after $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$1 downsampling. Reported results include 80.07% on digits $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$2, 86.2% on $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$3, 72.34% on $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$4, and 75.07% on $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$5 (Song et al., 5 Sep 2025). The paper attributes this to class-dependent confusion introduced by aggressive downsampling.

Energy accounting in the paper is explicitly dynamic unless otherwise stated. It defines

$$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$6

and states that the reported “energy for inference” in the comparison table is the dynamic energy of JJ switchings (Song et al., 5 Sep 2025). Two numerical values are given for dynamic energy per inference: 6.55 fJ in the abstract and conclusion, and $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$7 nJ in the comparison table, which is 1.31 fJ. The source identifies this as a discrepancy by approximately $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$8 and notes that the safest interpretation is that dynamic energy per inference lies in the low-single-digit femtojoule range (Song et al., 5 Sep 2025).

The same source also derives a static-energy estimate. If one inference takes 10 cycles at 3.02 GHz, then $$\frac{\partial \hat{z}}{\partial U} = \frac{1}{\pi \left(1 + (U\pi)^2\right)}.$$9 ns, and

$p_i[t] = \frac{e^{U_i[t]}}{\sum_j e^{U_j[t]}},$0

That static term is much larger than the reported dynamic few-fJ term, although the paper does not report a combined per-inference figure (Song et al., 5 Sep 2025). This distinction matters because SFQ biasing can dominate total system energy even when switching energy is exceptionally low.

For broader context, a related superconducting SNN accelerator reports 97.07% pre-pruning and 96.1% post-pruning accuracy on MNIST, 8.92 GHz throughput, approximately 5.01 pJ/inference for electronics only, and 1.5 nJ/inference including cooling to 4 K (Karamuftuoglu et al., 2024). SuperSNN’s fabricated chip instead emphasizes physical realizability under SFQ5ee area and pin constraints, with much lower network size and correspondingly reduced task scope (Song et al., 5 Sep 2025).

6. Limitations, misconceptions, and future directions

The immediate limitations are structural. I/O pins force $p_i[t] = \frac{e^{U_i[t]}}{\sum_j e^{U_j[t]}},$1 inputs and serial loading; routing congestion constrains fan-out and layer width; limited JJ area restricts synaptic matrix size; and static bias power remains significant even when dynamic JJ switching energy is extremely small (Song et al., 5 Sep 2025). The framework also acknowledges a possible training-hardware mismatch when pruning and quantization must be made aggressive enough to satisfy layout limits.

Several common misconceptions are addressed directly by the cited sources. One is terminological: SupraSNN is not SuperSNN; it is a distinct FPGA architecture, and its paper states that the term “SuperSNN” does not appear there (Ghavami et al., 11 Jun 2026). Another is energetic: the low-fJ numbers reported for SuperSNN refer to dynamic switching energy rather than total cryogenic system energy, and the paper itself highlights a discrepancy between the 6.55 fJ and 1.31 fJ figures (Song et al., 5 Sep 2025). A third is architectural: high-throughput superconducting SNN proposals are not automatically physically realizable within SFQ5ee pin-count and routing budgets, which is precisely the gap SuperSNN was introduced to close (Song et al., 5 Sep 2025).

The proposed scaling directions are concrete. On the I/O side, the paper suggests multiplexed or higher-bandwidth shift-register interfaces, cryo-CMOS interfaces, and 3D integration. On the density side, it points to denser JJ processes, more metal layers, more compact mutual inductors, and standardization of high fan-in primitives as library cells. On the algorithmic side, it suggests $p_i[t] = \frac{e^{U_i[t]}}{\sum_j e^{U_j[t]}},$2 inputs or on-chip preprocessing such as a small convolutional front-end, as well as on-chip learning and tunable synapses. On the clocking side, it suggests hierarchical clocks, including an H-tree for the shift-register, and refined LAGS/GALS hybrids (Song et al., 5 Sep 2025).

A plausible implication is that the next scaling frontier is not a single innovation in neuron dynamics or training, but coordinated progress in pin-limited ingress, interconnect topology, standard-cell support for high fan-in accumulation, and the static-power economics of SFQ biasing. In that sense, SuperSNN is best understood not only as a specific chip result, but as a design methodology for bringing superconducting SNNs from small circuit demonstrations to physically realizable integrated systems (Song et al., 5 Sep 2025).