Non-Volatile Capacitive Synapses

• Non-volatile capacitive synapses are devices that store synaptic weight as a persistent capacitance state through ferroelectric polarization.
• They enable charge-domain compute-in-memory architectures, offering near-zero static power loss, immunity to sneak paths, and BEOL-compatible integration.
• Advances include multilevel state stability, ultrafast non-destructive readout, and precise charge-domain computation for dense neuromorphic systems.

Searching arXiv for papers on non-volatile capacitive synapses and ferroelectric memcapacitors. Non-Volatile Capacitive Synapses are artificial synaptic elements in which the stored weight is encoded in a persistent capacitance state, or in a remanent polarization-controlled electrostatic state that is read as capacitance, rather than as a resistance. In the literature, this category spans idealized memcapacitive systems, ferroelectric non-volatile capacitors, ferroelectric memcapacitors, and closely related capacitor-derived devices used for charge-domain compute-in-memory. Their defining feature is that memory resides in an internal material state—typically ferroelectric polarization—so the synaptic state can persist after power removal and can be accessed with non-destructive small-signal readout. This distinguishes them from volatile capacitor nodes and from non-volatile resistive or magnetic synapses, while giving them a characteristic architectural profile: charge-domain vector-matrix multiplication, virtually zero static power loss, intrinsic immunity to sneak paths, and strong affinity for BEOL-oriented monolithic 3D integration (Pershin et al., 2013, Bhardwaj et al., 17 Aug 2025).

1. Conceptual definition and scope

The foundational formalization of a capacitive memory element as a synapse appears in the memcapacitive systems framework of Pershin and Di Ventra, where a voltage-controlled memcapacitive system is written as

$$V_C(t)=C^{-1}(x,q,t)\,q(t), \qquad \dot{x}=f(x,q,t).$$

Here, the charge $q(t)$ and voltage $V_C(t)$ are coupled through a state-dependent memcapacitance $C(x,q,t)$, and memory is stored in the internal state vector $x$ rather than in transient charge alone. In that formulation, a capacitive synapse is non-volatile when the internal state persists after the drive is removed, so synaptic weight is represented by capacitance rather than conductance (Pershin et al., 2013).

In the contemporary ferroelectric literature, the term encompasses several device classes. The 2025 perspective on capacitive in-memory computing identifies metal-ferroelectric-metal (MFM) memcapacitors, metal-ferroelectric-semiconductor (MFS) devices, FeFET-based capacitive synapses, and charge-shielding capacitors as the main families. Across these families, non-volatility arises from remanent ferroelectric polarization, while the observable synaptic variable is a capacitance state, a capacitive memory window, or an electrostatically modulated effective capacitance seen at the terminals (Bhardwaj et al., 17 Aug 2025).

It is also necessary to distinguish direct capacitive synapses from adjacent ferroelectric synapse classes. The BEOL-compatible HZO/WO$_x$ FeFET for synaptic weights stores state in ferroelectric polarization but reads it as channel resistance, and is therefore best understood as a non-volatile ferroelectric analog synapse closely connected to capacitive-memory concepts rather than as a direct two-terminal capacitive synapse (Halter et al., 2020). The hybrid FeMFET-CMOS analog synapse similarly combines a non-volatile FeMFET-based MSB path with a volatile 3T1C LSB path; it is synaptic and partially capacitive in implementation, but not a standalone non-volatile capacitive synapse in the strict two-terminal sense (Kazemi et al., 2020).

The category also borders broader electrostatic and charge-storage synapse concepts. Sliding-ferroelectric bilayer MoS$_2$ devices retain synaptic state through switchable interlayer polarization that modulates conductance at $V_G=0$, and protonic complex synapses retain state through coupled charge/proton diffusion variables. These are non-volatile synapses with strong capacitive or electrostatic character, but the source text explicitly notes that they are not classical standalone capacitor memories (Li et al., 2024, Zhang et al., 2024).

2. Physical mechanisms of weight storage

In ferroelectric non-volatile capacitors, the canonical physical mechanism is polarization-dependent modulation of the read capacitance. In the foundry 28 nm nvCap platform characterized cryogenically, the device uses the FeFET platform in a mode that exploits $C$–$V$ asymmetry under small-signal readout. Two non-volatile capacitance states are defined: LCS and HCS. With source and drain grounded and a small AC signal applied to the gate, positive polarization induces inversion in the channel and allows the full gate area to contribute to capacitance in HCS, whereas negative polarization causes depletion and limits capacitance mainly to the gate-to-source/drain overlap region in LCS. The result is a large memory window in capacitance, with an on/off capacitance ratio of about 25 at 0 V and 290 K, and about 10 in the pulse-based cryogenic read scheme at 77 K (Vadlamani et al., 28 Oct 2025).

A second route is partial ferroelectric switching in standalone FeCaps. In the HfO$q(t)$0/ZrO$q(t)$1 nanolaminate platform, partial domain switching produces intermediate polarization levels $q(t)$2 that the authors explicitly interpret as MemCapacitance states. The device integrates a 10 nm $q(t)$3 nanolaminate in a BEOL-compatible CMOS process and on thermal SiO$q(t)$4/Si, with the stack described as $q(t)$5. Full switching gives $q(t)$6, with $q(t)$7, but the synaptically relevant feature is that intermediate non-volatile states are obtained by varying $q(t)$8 and $q(t)$9, so weight can be stored as stable multilevel capacitance without destructive readout (Baigol et al., 2 Jun 2026).

Standalone ferroelectric memcapacitors extend this principle to explicit multibit analog storage. The TiN/HZO/TiN HfZrO memcapacitor demonstrates more than eight stable, reprogrammable capacitance states, corresponding to 3-bit encoding, within a non-volatile window of 24 pF. In this device, the capacitance depends on the polarization state of ferroelectric HZO, with the free-energy description

$V_C(t)$0

Binary programming sets HCS with a sweep to $V_C(t)$1 V and LCS with a sweep to $V_C(t)$2 V, while progressively increasing amplitudes access intermediate quasi-stable states. The optimized HZO-MS stack exhibits 8–9 reprogrammable capacitance states spanning about 118 pF down to 92 pF, and nanoscale PFM and EFM measurements resolve written polarization and charge states, including three distinct charge levels for a three-state write (Yadav et al., 13 Nov 2025).

3. Programming, readout, and plasticity

The programming and read mechanisms of non-volatile capacitive synapses are unusually varied because the same ferroelectric state can be interrogated either through conventional capacitance measurements or through transient regimes that avoid full capacitive charging. In the cryogenic nvCap study, the pulse-based read sequence is: erase pulse at $V_C(t)$3 V for $V_C(t)$4s, read sweep from $V_C(t)$5 V to $V_C(t)$6 V, program pulse at $V_C(t)$7 V for $V_C(t)$8s, then a second read sweep from $V_C(t)$9 V to $C(x,q,t)$0 V. This pulse-first scheme is used to read the capacitance window before charge trapping dominates, and at 77 K it reveals a clear capacitive memory window with an on/off ratio around 10 (Vadlamani et al., 28 Oct 2025).

A central practical issue is the bandwidth limit of standard non-destructive $C(x,q,t)$1–$C(x,q,t)$2 readout. In the HfO$C(x,q,t)$3/ZrO$C(x,q,t)$4 FeCap platform, the MemCapacitance window collapses above 1 MHz to 2 MHz, which constrains ordinary capacitive read speed. To circumvent this limit, the authors introduce a 20 ps non-destructive read methodology. When the read pulse width is shorter than the device RC time constant—stated as below 300 ps—the response becomes purely resistive and is governed by the polarization-dependent leakage current rather than by full capacitive charging. Using a single unipolar 20 ps pulse, the two programmed states are discriminated through the leaky-capacitor response, with read energy of approximately 14 fJ. The same platform reports nanosecond multilevel programming below 5 V, including 1 ns write operations (Baigol et al., 2 Jun 2026).

Pulse-mode behavior is especially important because memory arrays do not operate under seconds-long quasi-static sweeps. In the BEOL-compatible HZO/IWO nvCAP, pulse-mode characterization uses $C(x,q,t)$5 V program pulses, $C(x,q,t)$6 V erase pulses, and capacitance readout at 0.1 V and 1 MHz, typically about 1 s after each write. The study shows that $C(x,q,t)$7 is limited by lateral RC delay in the resistive amorphous oxide channel, while $C(x,q,t)$8 is strongly affected by incomplete erase and partial depletion. Pulse widths greater than $C(x,q,t)$9s are sufficient to reach $x$0 comparable to DC-sweep values, whereas $x$1 increases sharply for pulse widths below about $x$2s (Lee et al., 17 Dec 2025).

At the learning-rule level, the memcapacitive neural-network work showed that spike-timing-dependent plasticity can be implemented with double voltage pulses applied from presynaptic and postsynaptic sides. Their overlap creates a polarity-dependent effective voltage across the memcapacitor, producing long-term potentiation or long-term depression through thresholded memcapacitance change. This is conceptually important because it establishes that a capacitive weight need not be static memory only; it can also support activity-dependent synaptic plasticity in a native device-level update rule (Pershin et al., 2013).

4. Charge-domain computation and array architectures

The principal architectural role of non-volatile capacitive synapses is in charge-domain compute-in-memory. In the capacitive formulation, the programmed weight is the capacitance $x$3 rather than the conductance $x$4. The output is formed by charge transfer to a reference capacitor, with the relation

$x$5

or equivalently $x$6 in the descriptive form used in the perspective. The cryogenic nvCap work describes the same operation as a two-phase process: a charging phase, in which wordline voltages activate array capacitances and each cell stores charge according to its capacitance state and input voltage, followed by a discharge or charge-transfer phase, in which accumulated charge is transferred to a reference capacitor to implement weighted summation directly in the charge domain (Bhardwaj et al., 17 Aug 2025, Vadlamani et al., 28 Oct 2025).

This computational style is repeatedly contrasted with resistive crossbars. The perspective attributes to capacitive memories virtually zero static power loss, intrinsic immunity to sneak paths, selector-less crossbar operation, minimal IR drops, low read disturbance, and strong BEOL/3D integration compatibility. Because the computation is displacement-charge based rather than sustained-current based, no steady DC path is required during inference, and the interconnect currents are described as small transient currents rather than the larger currents characteristic of resistive arrays (Bhardwaj et al., 17 Aug 2025).

System precision is limited by charge-domain noise. The cryogenic nvCap study emphasizes the thermal-noise scaling

$x$7

and uses the standard relation

$x$8

to map signal-to-noise ratio to effective precision. In SPICE simulations of a 128 $x$9 128 capacitive crossbar using compact nvCap models, foundry PDK peripherals, and 9T telescopic op-amps, cooling from 290 K to 77 K improves ENOB from about 4 bits to about 5 bits for MAC operations. The array capacitances dominate the modeled noise contribution, while amplifier noise is neglected because it is much smaller than the array-induced noise (Vadlamani et al., 28 Oct 2025).

5. Reliability, nonidealities, and precision limits

Retention and endurance are decisive because a synaptic state that is non-volatile in principle may still be operationally unstable. The cryogenic nvCap work reports that HCS decay under 0.1 V DC read stress is much smaller at 77 K than at 290 K, attributing the improvement to thermally activated domain-wall depinning, suppressed thermal activation, reduced depolarization, and improved polarization retention (Vadlamani et al., 28 Oct 2025). In the HfO$_x$0/ZrO$_x$1 FeCap platform, partial switching enhances endurance above $_x$2 cycles, with about $_x$3 cycles reported at $_x$4 V and up to $_x$5 cycles at $_x$6 V, while projected retention is 10 years with an MC ratio above 6% (Baigol et al., 2 Jun 2026). The HZO memcapacitor reports retention beyond $_x$7 s and stable operation over $_x$8 cycles for the optimized stack (Yadav et al., 13 Nov 2025). The oxide-channel BEOL nvCAP demonstrates non-destructive read operation for more than $_x$9 read stress cycles at $_2$0 V (Lee et al., 17 Dec 2025).

Several nonidealities recur across platforms. In the cryogenic nvCap, the quasi-static $_2$1–$_2$2 memory window at 77 K shrinks from roughly 2 V to 0.5 V and shifts to the right because lower intrinsic carrier density requires larger gate voltage to induce inversion; a separate pulse-sequence test indicates that the narrowing is strongly affected by carrier trapping in the gate stack rather than by simple loss of ferroelectric switching (Vadlamani et al., 28 Oct 2025). In the HfO$_2$3/ZrO$_2$4 FeCap, the MC window collapses above 1–2 MHz under conventional capacitive readout, which is a direct bandwidth limit for standard small-signal sensing (Baigol et al., 2 Jun 2026). In the HZO memcapacitor, programming is asymmetric, with positive sweeps beginning around +1 V and negative sweeps around $_2$5 V, and the mid-window states show the largest variability because domain activity is strongest there (Yadav et al., 13 Nov 2025). In the oxide-channel nvCAP, larger overlap improves retention but worsens endurance, smaller device area improves endurance, and operation at 85 $_2$6C accelerates decay of both $_2$7 and $_2$8 (Lee et al., 17 Dec 2025).

The perspective paper frames these device observations as a precision problem at the architectural level. Effective analog resolution depends on the capacitive memory window, device-to-device and cycle-to-cycle variation, charge-transfer noise, amplifier offset, $_2$9 noise, random telegraph noise, hysteresis, and readout linearity; without mitigation, practical precision may be limited to roughly 2–4 bits. It therefore emphasizes circuit-level mitigation through correlated double sampling, offset-cancelled amplifiers, feedback sensing, differential sensing, program-and-verify, and hardware-aware training (Bhardwaj et al., 17 Aug 2025).

6. Integration trajectories, applications, and boundaries of the category

Non-volatile capacitive synapses are strongly associated with BEOL-compatible materials and with monolithic integration above CMOS. The direct-capacitive platforms described in the recent literature are summarized below.

Platform	Weight encoding and readout	Reported characteristics
Ferroelectric nvCap on foundry 28 nm (Vadlamani et al., 28 Oct 2025)	HCS/LCS from polarization-dependent channel modulation; small-signal capacitance read	On/off ratio about 25 at 290 K and about 10 at 77 K; 128 $V_G=0$0 128 MAC ENOB about 4 bits to about 5 bits
HfO$V_G=0$1/ZrO$V_G=0$2 FeCap (Baigol et al., 2 Jun 2026)	Partial ferroelectric switching yields MemCapacitance states; ultrafast leakage-based NDRO	1 ns write below 5 V; 20 ps non-destructive read; endurance up to $V_G=0$3 cycles
TiN/HZO/TiN memcapacitor (Yadav et al., 13 Nov 2025)	Multilevel ferroelectric capacitance states in standalone MFM stack	More than eight stable states; 24 pF non-volatile window; retention $V_G=0$4 s; endurance $V_G=0$5 cycles
HZO/IWO oxide-channel nvCAP (Lee et al., 17 Dec 2025)	$V_G=0$6 from ferroelectric-oxide-channel coupling under pulse mode	Highest measured $V_G=0$7; NDRO for more than $V_G=0$8 read cycles

These devices are relevant to several application domains. The cryogenic nvCap work explicitly identifies high-performance data center accelerators, quantum computing peripheral circuitry, and aerospace electronics as low-temperature contexts in which improved retention and ENOB are directly attractive (Vadlamani et al., 28 Oct 2025). The HZO memcapacitor demonstrates circuit-level viability by tuning the cutoff frequency of a high-pass filter by about 5 kHz overall, from 45.5 kHz to 41.1 kHz between programmed states, supporting adaptive RF filters, reconfigurable analogue front-ends, and neuromorphic electronics (Yadav et al., 13 Nov 2025). The oxide-channel nvCAP and the broader capacitive-CIM perspective both emphasize monolithic 3D integration above CMOS as a scaling route for dense AI hardware (Lee et al., 17 Dec 2025, Bhardwaj et al., 17 Aug 2025).

The boundary of the category remains important. Ferroelectric transistor synapses such as the HZO/WO$V_G=0$9 FeFET and the hybrid FeMFET-CMOS circuit retain state through ferroelectric polarization but read it as conductance or current, not as capacitance; they are closely related, and in some architectures they may interoperate with capacitive arrays, but they are not direct capacitive synapses in operation (Halter et al., 2020, Kazemi et al., 2020). Likewise, nanomagnetic racetrack synapses and skyrmion-based SNN synapses are non-volatile synapses whose state is stored in magnetic domain-wall position or magnetic texture rather than in capacitance, and thus fall outside the capacitive class despite serving a comparable architectural role (Alam et al., 2023, Das et al., 2024).

Taken together, the literature defines non-volatile capacitive synapses as a distinct hardware direction: weight is stored in capacitance or in a polarization-governed capacitive response; computation proceeds in the charge domain; and practical usefulness depends on co-optimization of ferroelectric material physics, interface engineering, pulse protocol, sensing circuitry, and array architecture. The central research trajectory is therefore not merely to demonstrate non-volatility, but to enlarge the capacitive memory window, stabilize multilevel states, extend non-destructive read bandwidth, and preserve precision under realistic array-level noise and variability (Bhardwaj et al., 17 Aug 2025).