Gm-C Dynamic Amplifiers in Neuromorphic & Clocked Designs

• Gm-C dynamic amplifiers are circuits where a transconductance stage drives a capacitor, setting exponential decay for continuous-time neuromorphic applications or dynamic gain in clocked systems.
• They can operate with feedback for analog exponential decay or in an open-loop clocked mode to achieve precise gain determined by the Gm/C ratio and sampling interval.
• Key design trade-offs include achieving ultra-low transconductance for long time constants versus ensuring high linearity and temperature stability in clocked data converter implementations.

Searching arXiv for the cited papers to ground the article in the provided research. Tool call: arxiv_search({"query":"id:(Mayr et al., 2014) OR \"OTA based 200 GΩ resistance on 700 μm2 in 180 nm CMOS for neuromorphic applications\"","max_results":5,"sort_by":"relevance"}) A Gm-C dynamic amplifier is a circuit in which a transconductance stage, characterized by $G_m$ or $g_m$, drives a capacitor so that voltage gain, temporal dynamics, or both are determined directly by the $G_m/C$ ratio. In the cited literature, the term appears in two distinct but related senses. In neuromorphic continuous-time circuits, an operational transconductance amplifier (OTA) is placed in feedback around a capacitor to realize exponential rise and decay with time constant $\tau = C/g_m$, so that extremely small transconductance values emulate very large resistances and long time constants (Mayr et al., 2014). In clocked data-converter-oriented circuits, a Gm-C dynamic amplifier is an open-loop dynamic stage that charges a capacitor only during an amplification phase, with differential gain approximately $A = G_m T / C$, where $T$ is the effective amplification interval (Yang et al., 20 Aug 2025). Both interpretations are centered on the same principle: a current proportional to input voltage is integrated on capacitance, but they differ in whether operation is continuous-time or clocked, whether feedback is present, and whether the primary objective is long biological time constants or residue amplification.

1. Conceptual scope and governing relations

The continuous-time formulation uses an OTA as a conductance element. In a gm-C configuration, the OTA is used in feedback around a capacitor $C$, producing exponential decay with

$\tau = \frac{C}{g_m}$

and an effective resistance

$R_{\text{eq}} \approx \frac{1}{g_m}.$

At $g_m = 5~\text{pS}$, this corresponds to $g_m$0, and with $g_m$1 fF the time constant is approximately $g_m$2 ms; for $g_m$3 pF, $g_m$4 approaches $g_m$5 ms (Mayr et al., 2014). In this usage, the Gm-C dynamic amplifier is primarily a time-constant generator.

The clocked formulation defines gain in the time domain. The output is described as

$g_m$6

so that

$g_m$7

Here the amplifier is open-loop Gm-C, uses clocked switches to alternate between reset and amplification phases, and charges an output capacitor only during a defined time window $g_m$8 (Yang et al., 20 Aug 2025). In this usage, the Gm-C dynamic amplifier is a dynamic gain element rather than a continuous-time decay cell.

A common misunderstanding is to treat all Gm-C dynamic amplifiers as continuous-time OTAs. The literature shows otherwise. One paper explicitly states that the clocked implementation is not a traditional continuous-time OTA and is closer to a switched-capacitor or time-interleaved residue amplifier used in pipelined SAR ADCs, whereas the neuromorphic implementation is explicitly asynchronous and continuous-time (Yang et al., 20 Aug 2025).

2. Continuous-time gm-C dynamic amplifiers for long time constants

In the neuromorphic realization, the design target is ultra-low transconductance so that moderate on-chip capacitances can produce long decays. The reported OTA achieves $g_m$9 in only 700 $G_m/C$0 in 180 nm CMOS, giving an equivalent resistance near 200 G$G_m/C$1 (Mayr et al., 2014). This directly addresses the requirement that neuromorphic systems may need >100 such time-constant circuits on a single chip.

The dynamic behavior follows a first-order differential equation,

$G_m/C$2

with solution

$G_m/C$3

The paper reports measured exponential decay with $G_m/C$4 fF and $G_m/C$5 pS, yielding an extracted time constant of about $G_m/C$6 ms, consistent with $G_m/C$7 (Mayr et al., 2014). Rising and falling edges were fitted with exponentials, and the authors note that nonlinearity has no significant influence on the decay waveform.

The stated application domain explains why such a circuit is termed a dynamic amplifier despite modest linearity by conventional analog standards. The long time constants of 10–100+ ms are essential for membrane time constants, presynaptic adaptation, postsynaptic current (PSC) traces), synaptic learning rules such as spike-timing dependent plasticity, and driving neuromorphic memristor arrays (Mayr et al., 2014). In these contexts, exact THD is less important than reliable exponential wave shaping over biologically relevant time scales.

The same OTA can also be used without feedback as a voltage-to-current converter. In that mode it forms PSC-like waveforms, whereas in feedback around a capacitor it realizes an exponential state variable. This suggests that, in neuromorphic practice, the Gm-C dynamic amplifier is often a multifunctional kernel generator rather than a narrowly defined gain stage.

3. Clocked open-loop Gm-C dynamic amplifiers

The 2025 design uses the term in a more specific sampled-data sense. The amplifier is controlled by clock phases, is reset in one phase, and amplifies only during another. During the amplification phase, switches connect the differential pair currents to the output capacitor, while during the reset phase internal and output nodes are discharged or shorted so that residual charge is removed (Yang et al., 20 Aug 2025).

Its top-level architecture has two parts. The main Gm-C stage is implemented as a composite differential pair, formed by two asymmetric differential pairs, and drives a capacitor where the output voltage is developed. The constant-gm bias circuit defines a temperature- and supply-insensitive transconductance and mirrors this bias to the main-stage tails (Yang et al., 20 Aug 2025). Because the topology is open-loop, the text states that feedback-stability issues typical of OTAs do not apply; instead, accuracy depends on gm linearity and gm stability.

The differential current generated by the main stage obeys

$G_m/C$8

and for constant input over the amplification interval,

$G_m/C$9

Thus the gain is determined jointly by device transconductance, capacitor value, and timing (Yang et al., 20 Aug 2025). The paper further states that the output is sampled at the falling edge of $\tau = C/g_m$0, which places the circuit squarely in the class of clocked dynamic residue amplifiers rather than continuous-time filters.

This clocked meaning of Gm-C dynamic amplifier is particularly relevant when gain must be maintained over a narrowly specified differential input range. The cited implementation targets nearly constant gain over $\tau = C/g_m$1 mV to $\tau = C/g_m$2 mV and combines gm shaping with constant-gm biasing to suppress both nonlinear gain roll-off and temperature or supply drift (Yang et al., 20 Aug 2025).

4. Core circuit techniques

Two distinct architectural strategies are documented in the cited works.

In the ultra-low-$\tau = C/g_m$3 neuromorphic OTA, the architecture combines three techniques: a PMOS differential pair with current splitting, source degeneration (local negative feedback), and series-parallel current mirrors for huge current down-scaling (Mayr et al., 2014). The input pair M1/M2 has

$\tau = C/g_m$4

and each branch feeds a current splitter that takes only a $\tau = C/g_m$5 fraction of the differential-pair drain current. Source degeneration is implemented by transistors M3 and M4 operating in the linear region. The mirror network then applies an additional scaling of either $\tau = C/g_m$6 or $\tau = C/g_m$7. The total small-signal transconductance is given as

$\tau = C/g_m$8

The design intent is explicit: keep the gm-critical devices in strong inversion with bias currents in the 1–10 $\tau = C/g_m$9A range, and confine weak inversion operation to the final scaling stage, where currents are already extremely small (Mayr et al., 2014).

In the high-linearity clocked amplifier, the main technique is gm shaping through two asymmetric differential pairs (Yang et al., 20 Aug 2025). A single asymmetric pair uses transistor ratios $A = G_m T / C$0 and $A = G_m T / C$1 with $A = G_m T / C$2, which shifts the $A = G_m T / C$3-versus-input curve horizontally. Two mirrored asymmetric pairs are then summed so that one pair’s $A = G_m T / C$4 peak shifts to positive $A = G_m T / C$5 and the other to negative $A = G_m T / C$6, yielding a composite transconductance that is nearly flat around zero input. The total transconductance is described as

$A = G_m T / C$7

The bias path then uses a constant-gm bias circuit based on transistors M24, M25, and resistor R1. The paper states that the resulting transconductance depends only on transistor geometry ratios and $A = G_m T / C$8, not on temperature or supply voltage to first order (Yang et al., 20 Aug 2025).

A useful contrast emerges between the two designs. One attains extremely small $A = G_m T / C$9 through cascaded reduction mechanisms while preserving input swing and area efficiency; the other shapes $T$0 and stabilizes it against temperature and $T$1 so that sampled gain remains linear and repeatable. This suggests that “Gm-C dynamic amplifier” identifies a principle of operation rather than a single canonical topology.

5. Performance, operating limits, and trade-offs

The two implementations prioritize different figures of merit.

For the neuromorphic OTA, key measured metrics include a nominal $T$2 pS transconductance at $T$3 and $T$4, a measured mean of $T$5 pS with $T$6 pS across 65 instances on 13 chips, and a maximum observed value of about 10 pS (Mayr et al., 2014). The reported linear range is approximately 1.2 V input swing at 20% linearity error ($T$7 metric). Flicker noise dominates in the 1 Hz–1 kHz band, with measured noise of 950 $T$8 and equivalent noise density 30 $T$9. The input-referred offset over the same 65 instances has mean 9.9 mV and standard deviation 75 mV. Power is described as being in the few-$C$0W range, with the text giving both the expression $C$1 and a cited value of 2.7 $C$2W at $C$3 and $C$4 V, while also noting an arithmetic estimate of 5.4 $C$5W under the same nominal quantities (Mayr et al., 2014). The paper explicitly acknowledges this discrepancy.

For the clocked high-linearity design, the principal reported numbers are a nearly constant gain over $C$6 mV to $C$7 mV, THD = 70.5 dB for the proposed amplifier, and THD = 49.3 dB for the traditional amplifier under the stated sinusoidal-input and FFT conditions (Yang et al., 20 Aug 2025). Under $C$8 supply fluctuation, temperature sweep from $C$9 to $\tau = \frac{C}{g_m}$0, and 1 mV differential input, the gain distribution has standard deviation 262m and range 15.1 to 16.3, whereas the traditional Gm-C dynamic amplifier has standard deviation 1.9 and range 13 to 19.5 (Yang et al., 20 Aug 2025).

The trade-offs are correspondingly different. The neuromorphic design explicitly sacrifices THD performance and accepts 20% nonlinearity because waveform exactness is secondary to area, swing, and time constant density (Mayr et al., 2014). The clocked design accepts greater circuit complexity, including additional input devices, a constant-gm bias cell, and common-gate isolation devices, in exchange for flatter gain and reduced temperature and supply sensitivity (Yang et al., 20 Aug 2025).

6. Applications, comparison points, and design implications

The neuromorphic paper identifies three concrete application classes. First, the OTA-C cell generates exponential voltage traces for synaptic learning rules, including windows of the form

$\tau = \frac{C}{g_m}$1

Second, when used as a voltage-to-current converter, it generates PSCs of the form

$\tau = \frac{C}{g_m}$2

which are integrated on the membrane capacitance. Third, the OTA-C output can directly drive voltage-dependent memristors, for which the reported 1.2 V output swing is compatible with thresholds described in related work (Mayr et al., 2014). The chip context includes a neuron and synapse matrix implementing a novel plasticity rule and test structures for CMOS-integrated memristors.

The same paper also situates its OTA against other low-$\tau = \frac{C}{g_m}$3 circuits. It reports an area of 0.0007 mm$\tau = \frac{C}{g_m}$4, described as 15× smaller than the smallest listed competitor, while retaining a 5–50 pS transconductance range, 30 $\tau = \frac{C}{g_m}$5 noise density, and a comparatively large 1.2 V swing (Mayr et al., 2014). The comparison is careful to note that other designs often use stricter linearity metrics such as THD $\tau = \frac{C}{g_m}$6–5% or $\tau = \frac{C}{g_m}$7, whereas this OTA uses $\tau = \frac{C}{g_m}$8. The implication is not that the device is generically superior, but that it is specifically optimized for neuromorphic wave shaping.

The 2025 paper extracts a different set of design guidelines. It recommends gm shaping through two asymmetric pairs for linearity, a constant-gm bias cell for temperature and supply stability, explicit design through the relation $\tau = \frac{C}{g_m}$9, reset switches to suppress memory and charge sharing, and one-time post-fabrication calibration through $R_{\text{eq}} \approx \frac{1}{g_m}.$0 or alternative bias trimming to handle process variation (Yang et al., 20 Aug 2025). This suggests that, in sampled-data environments, the main concern shifts from ultra-low transconductance density to predictability of gain across input amplitude and PVT.

Taken together, the cited works present the Gm-C dynamic amplifier as a broad circuit class unified by capacitor integration of a transconductance-generated current, but differentiated by operating regime and optimization target. In one branch, the central objective is ultra-low $R_{\text{eq}} \approx \frac{1}{g_m}.$1, large effective resistance, and long exponential time constants in minimal silicon area (Mayr et al., 2014). In the other, the central objective is open-loop dynamic gain with high linearity and high temperature and power supply voltage stability through asymmetric-pair gm shaping and constant-gm biasing (Yang et al., 20 Aug 2025).