2D-Weighted Capacitor Array in Charge-Domain CIM

• 2D-weighted capacitor array is a binary-weighted capacitor matrix that encodes input–weight bit products over two dimensions for efficient charge-domain computation.
• This architecture enables a hybrid digital-analog partition in SRAM-CIM, reducing ADC precision requirements while enhancing complex-number MAC performance.
• The design finds practical applications in high-density SRAM-CIM macros and influences diverse implementations in printed electronics, graphene varactors, and textile sensors.

A 2D-weighted capacitor array is, in the most direct contemporary usage, a binary-weighted capacitor matrix whose weighting depends on two bit-significance dimensions and that is used for charge-domain computation. The clearest explicit instantiation appears in a 28 nm digital/analog hybrid SRAM-CIM macro for complex-number multiply-accumulate (MAC), where a “2D binary-weighted capacitor array” receives bitwise input–weight products and performs DAC-less analog accumulation of lower-significance partial products (Konno et al., 25 Aug 2025). Related literature studies several adjacent concepts—planar capacitor cells with density-dependent capacitance, nested multi-electrode capacitive cells, time-multiplexed switched-capacitor multipliers, distributed RC textile sensors, graphene varactor sheets, and printed 2D-material capacitor banks—that illuminate alternative physical meanings of two-dimensional weighting, although many of these works do not use the exact term “2D-weighted capacitor array” (Skinner et al., 2010, Grebel, 2017, Lee et al., 2016, Gu et al., 2011, AbdelGhany et al., 2016, Worsley et al., 2018).

1. Definition and conceptual scope

In the SRAM-CIM literature, the term denotes a capacitor array in which the effective weight is distributed over two dimensions associated with the two multiplicand bit indices. The stated purpose is to implement “a DAC-less, charge-domain, bit-significance-weighted summation of input–weight partial products,” so that analog CIM is used only for lower-significance multiplication terms while digital CIM handles the upper-bit group (Konno et al., 25 Aug 2025). The paper describes the array as “a 2D binary-weighted capacitor array (2D-Array) based on the product of input (operand 1) and weight (operand 2),” and emphasizes that this eliminates the input DACs required by conventional binary-weighted capacitor-based CIM (Konno et al., 25 Aug 2025).

This direct usage is narrower than the broader family of two-dimensionally organized capacitor systems in the literature. A plausible implication is that “2D-weighted capacitor array” can also serve as a descriptive umbrella for architectures in which capacitance values, coupling coefficients, or spatial response functions are distributed across two spatial dimensions. The literature supports several such interpretations: local planar cells with density-tunable capacitance in low-density two-dimensional electron gases (2DEGs), nested multi-electrode capacitor-within-capacitor cells, distributed RC fiber arrays functioning as 2D touch sensors, and globally biased 2D graphene varactor sheets (Skinner et al., 2010, Grebel, 2017, Gu et al., 2011, AbdelGhany et al., 2016).

A concise classification of the main interpretations appearing in the cited works is given below.

Class	Weighting mechanism	Relation to the exact term
SRAM-CIM hybrid macro	2D binary weighting over input-bit and weight-bit products	Direct use (Konno et al., 25 Aug 2025)
Passive switched-cap matrix multiplier	Time-multiplexed capacitor-coded weights	Related but not fully spatial 2D (Lee et al., 2016)
BSCHA SRAM-CIM accumulator	Per-column temporal binary-weighted charge sharing	Explicitly not a literal 2D weighted capacitor array (Yang et al., 29 May 2026)
2DEG planar cells	Density-dependent local capacitance $C(n)$	Local constitutive model for array cells (Skinner et al., 2010)
CWC multi-electrode cells	Induction and field redistribution	Tunable cell, not strict 2D capacitor matrix (Grebel, 2017)
Distributed textile fibers / graphene sheets / printed stacks	Spatially distributed or tiled capacitance	Physical 2D array interpretations (Gu et al., 2011, AbdelGhany et al., 2016, Worsley et al., 2018)

2. Charge-domain operation in the direct SRAM-CIM realization

The defining direct realization is a 64 kb SRAM-CIM prototype composed of eight complex CIM-SRAM units, implemented in 28 nm CMOS, in which the 2D-weighted capacitor array is the key analog structure of the ACIM path (Konno et al., 25 Aug 2025). In this architecture, the SRAM stores real and imaginary weights, pass transistor logic generates multi-bit input–weight bit-products, and the 2D-weighted capacitor array performs charge-domain summation of the analog-assigned lower-significance terms before a 7-bit SAR ADC digitizes the result (Konno et al., 25 Aug 2025).

The two dimensions correspond to the two multiplicand bit positions. The paper states that the weighting is “based on the product of input and weight,” and the intended significance is therefore the binary product significance $2^{i+j}$ of each bit-pair contribution (Konno et al., 25 Aug 2025). A plausible idealized interpretation is that the ACIM path computes

$$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$

where $\mathcal{A}$ is the set of bit-pairs assigned to analog processing. The paper does not print this equation explicitly, but it follows directly from the described “Ideal 2D-Weight Table” and the stated role of the 2D binary-weighted capacitor matrix (Konno et al., 25 Aug 2025).

The physical computation is charge-domain accumulation. A plausible idealized form is

$$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$

with $b_{ij}=I[i]W[j]$ and $C_{ij}\propto 2^{i+j}$, followed by charge sharing onto a total capacitance $C_{\text{tot}}$. This suggests an output voltage

$$V_{\text{out}}=\frac{1}{C_{\text{tot}}}\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij}.$$

The paper’s explicit contribution is the architectural statement that the capacitor values encode binary significance across two dimensions, not a closed-form symbolic derivation of the node equation (Konno et al., 25 Aug 2025).

Two implementation choices limit array growth. First, signed-magnitude format is used, so the MSBs represent sign bits and the row and column associated with those sign bits are reduced (Konno et al., 25 Aug 2025). Second, “the use of split-DAC effectively reduces the number of CAPs,” indicating segmentation of the capacitor network rather than a monolithic full binary matrix (Konno et al., 25 Aug 2025).

3. Hybrid digital/analog partition and complex-number MAC

The hybrid architecture divides the multiply-accumulate operation between digital CIM and analog CIM. The upper-bit group is assigned to DCIM and the remaining groups to ACIM, because the paper finds that the top three MAC result groups account for about half of the total contribution to output accuracy (Konno et al., 25 Aug 2025). The explicit consequence is that the analog path can be restricted to lower-significance terms, reducing the required ADC precision to 7 bits (Konno et al., 25 Aug 2025).

The macro supports complex-number computation with

$I(k)=I_r(k)+jI_i(k), \qquad W(k)=W_r(k)+jW_i(k),$

and computes

$2^{i+j}$0

in parallel real and imaginary paths (Konno et al., 25 Aug 2025). The architecture therefore maps the real part to $2^{i+j}$1 and the imaginary part to $2^{i+j}$2, with sign handling performed through polarity control of the analog reference: “VREFCLK toggles direction according to SIGNCLK generated by Sign CKGEN to change the polarity of the analog voltage converted by the ADC” (Konno et al., 25 Aug 2025).

This complex arithmetic function distinguishes the 2D-weighted capacitor array from simpler analog accumulation structures. In related work, complex CIM commonly requires either duplicated weights for parallel partial-product computation or sequential evaluation of the cross terms, increasing area or latency. The cited macro instead co-locates real and imaginary weights in custom 6T CIM-SRAM and uses the 2D-weighted capacitor array only where analog accumulation is most favorable (Konno et al., 25 Aug 2025).

The broader switched-capacitor literature reaches similar goals through different topologies. A passive switched-capacitor matrix multiplier performs matrix-vector multiplication $2^{i+j}$3 by time-multiplexed charge sampling and redistribution onto an accumulation capacitor shared with a 6 b SAR ADC, but it is “not a fully spatially instantiated 2D capacitor crossbar” (Lee et al., 2016). Likewise, a 256×128 SRAM-CIM macro with a charge-sharing-based weighted accumulator performs binary-weighted temporal accumulation using two equal capacitors $2^{i+j}$4 and $2^{i+j}$5 plus bitline parasitic capacitance $2^{i+j}$6, and explicitly “does not implement a literal 2D weighted capacitor array” (Yang et al., 29 May 2026). These contrasts clarify that the defining feature of the 2D-weighted capacitor array is not merely charge-domain weighting, but the explicit two-dimensional binary significance mapping of bit-pair products (Konno et al., 25 Aug 2025).

4. Circuit realization, density, and measured characteristics

The 28 nm prototype reports an active macro area of $2^{i+j}$7, memory density of $2^{i+j}$8, throughput of $2^{i+j}$9, and energy efficiency of $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$0 (Konno et al., 25 Aug 2025). The paper attributes practical feasibility to an aggressively compact capacitor implementation: the unit capacitor is a 48 aF M7–M7 fringe capacitor with area $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$1, about $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$2 of the minimum 2 fF MOM capacitor offered by the foundry (Konno et al., 25 Aug 2025).

The hybrid partition is explicitly motivated by mismatch and linearity. The calculated mismatch of the 48 aF unit capacitor is $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$3 rms, but the reduced analog precision requirement allows a 7-bit binary CDAC whose LSB is composed of 16C, giving a DNL of $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$4 LSB rms and meeting the linearity requirements (Konno et al., 25 Aug 2025). The reported complex-MAC RMS error is $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$5 without calibration, with almost no gain error and max INL evaluated at zero crossing while sweeping the inputs with weights fixed at $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$6 (Konno et al., 25 Aug 2025).

The floorplan places both the 2D-weighted capacitor array and the ADC CDAC above the custom CIM-SRAM array, and the paper states that this improves density and matching (Konno et al., 25 Aug 2025). The reported power breakdown includes approximately $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$7 for 6T CIM-SRAM and ACIM, $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$8 for DCIM, $$S_{\text{ACIM}}=\sum_{(i,j)\in\mathcal{A}} I[i]\,W[j]\,2^{i+j},$$9 for the ADC CDAC, and $\mathcal{A}$0 for the 2D-weighted capacitor array (Konno et al., 25 Aug 2025).

A distinct printed-electronics line of work provides a materially different array platform. Inkjet-printed graphene/hBN/graphene capacitors show an areal capacitance of $\mathcal{A}$1 for dielectric thickness $\mathcal{A}$2, dielectric constant $\mathcal{A}$3, and breakdown field $\mathcal{A}$4, averaged across more than 100 devices (Worsley et al., 2018). That work supports area-coded weighting and parallel composition of printed unit capacitors, but its reported average yield of $\mathcal{A}$5, representative $\mathcal{A}$6, and frequency-dependent $\mathcal{A}$7 imply a different design regime from dense CMOS charge-redistribution arrays (Worsley et al., 2018).

5. Related physical interpretations of two-dimensional weighting

Several works study capacitor arrays or spatially distributed capacitive media that do not use the exact SRAM-CIM meaning of “2D-weighted capacitor array,” but they are important for the term’s broader technical ecology.

A plane capacitor with a low-density 2DEG on one or both electrodes can exhibit capacitance larger than the geometric capacitance $\mathcal{A}$8 because Coulomb correlations reduce the effective thickness $\mathcal{A}$9 below the physical separation $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$0 (Skinner et al., 2010). For a locally uniform cell, the paper gives

$$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$1

and shows that in the regime $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$2,

$$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$3

with a clean-system upper bound $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$4 set by the effective Bohr radius $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$5 (Skinner et al., 2010). The paper is written for a single planar capacitor, but it explicitly suggests use as a local constitutive law for arrays of planar cells, provided fringing, nonuniformity, coupling, and disorder are treated separately (Skinner et al., 2010).

A “capacitor-within-capacitor” introduces inner or outer gate electrodes that redistribute electric field and induced charge, making the effective terminal capacitance tunable and, in experiments, larger than that of an ordinary two-plate counterpart by roughly $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$6–$$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$7 in several dielectric and ionic-liquid tests (Grebel, 2017). The authors stress that the effect is “purely linear and relies on induction,” and that accurate modeling requires a capacitance-matrix viewpoint rather than only lumped series/parallel cartoons (Grebel, 2017). This suggests a multi-terminal local cell rather than a simple independently weighted unit.

A fully woven touchpad based on soft capacitor fibers realizes a different type of spatial weighting: each fiber behaves as a distributed RC ladder, and when multiple fibers are woven in parallel and polled individually, the textile functions as a two-dimensional touch sensor (Gu et al., 2011). The fibers have typical capacitance $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$8, and the design rule stated by the paper is that “a short fiber with larger capacitance per unit length and higher resistivity will perform better at frequency around 1kHz” (Gu et al., 2011). Here the “weight” is position-dependent distributed attenuation rather than a binary capacitor code.

Suspended graphene varactors provide yet another physical interpretation. Arrays of at least $$Q_{\text{sum}}=\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij},$$9 suspended graphene membranes form a globally biased 2D array of tunable capacitors with areal capacitance density $b_{ij}=I[i]W[j]$0, total tunable capacitance $b_{ij}=I[i]W[j]$1, and $b_{ij}=I[i]W[j]$2 capacitance tuning at $b_{ij}=I[i]W[j]$3 (AbdelGhany et al., 2016). The total capacitance is the parallel sum of many unit cells, but the demonstrated device is globally tuned rather than independently weighted (AbdelGhany et al., 2016). A plausible implication is that weighting could be introduced through segmentation, local biasing, geometry variation, or membrane-count variation, all of which are discussed qualitatively in the paper (AbdelGhany et al., 2016).

6. Capacitance matrices, coupling, and extraction methodology

For array design, weighting is inseparable from parasitic self- and mutual capacitance. A dedicated unequal-disk analysis generalizes Love’s equation to two coaxial disks of radii $b_{ij}=I[i]W[j]$4 and $b_{ij}=I[i]W[j]$5, separation $b_{ij}=I[i]W[j]$6, and ratio $b_{ij}=I[i]W[j]$7, and derives the full $b_{ij}=I[i]W[j]$8 capacitance matrix in the short- and large-gap limits (Paffuti et al., 2016). In the short-gap regime, the leading divergence is controlled by the smaller disk: $b_{ij}=I[i]W[j]$9 with finite $C_{ij}\propto 2^{i+j}$0-dependent corrections to $C_{ij}\propto 2^{i+j}$1, $C_{ij}\propto 2^{i+j}$2, and $C_{ij}\propto 2^{i+j}$3 (Paffuti et al., 2016). The paper’s central design insight is that the smallest radius controls the strongest short-gap divergence, while asymmetry enters through finite fringe corrections, making it a useful reduced-order model for geometrically weighted circular array elements (Paffuti et al., 2016).

For repeated planar arrays over a common plate, fast Laplace-based extraction gives a local coupling stencil. In planar silicon pixel analogues, a 3D nine-pixel neighborhood is characterized by $C_{ij}\propto 2^{i+j}$4 to the backplane, orthogonal neighbor couplings $C_{ij}\propto 2^{i+j}$5 and $C_{ij}\propto 2^{i+j}$6, and diagonal coupling $C_{ij}\propto 2^{i+j}$7, with total interpixel capacitance

$C_{ij}\propto 2^{i+j}$8

(Assiouras et al., 2020). For square $C_{ij}\propto 2^{i+j}$9-pitch pixels, the reported orthogonal coupling decreases from about $C_{\text{tot}}$0 at $C_{\text{tot}}$1 gap to about $C_{\text{tot}}$2 at $C_{\text{tot}}$3 gap, while diagonal coupling decreases from about $C_{\text{tot}}$4 to about $C_{\text{tot}}$5 over the same range (Assiouras et al., 2020). This shows that nearest-neighbor coupling dominates, but diagonal terms are not negligible.

Modern extraction in heterogeneous dielectric stacks can also be framed through random-walk solvers. DeepRWCap accelerates floating-random-walk capacitance extraction by predicting Poisson kernels, gradient kernels, signs, and magnitudes of weights in local transition cubes, and reports a mean relative error of $C_{\text{tot}}$6 against Raphael on self-capacitance estimation of 10 industrial designs spanning 12 to 55 nm nodes, with an average $C_{\text{tot}}$7 speedup over Microwalk (Rodriguez et al., 10 Nov 2025). The underlying formulation is the capacitance-matrix relation

$C_{\text{tot}}$8

so the method is directly relevant to weighted capacitor array layouts even though the paper’s validated benchmark is self-capacitance rather than full many-body array matrices (Rodriguez et al., 10 Nov 2025).

7. Limitations, misconceptions, and design consequences

A recurring misconception is that any capacitor array with multiple dimensions is a “2D-weighted capacitor array.” The literature does not support such flattening. The 28 nm SRAM-CIM work uses the term specifically for a capacitor matrix whose values encode two-dimensional bit significance of input–weight products (Konno et al., 25 Aug 2025). By contrast, the BSCHA macro uses only two equal-valued explicit capacitors per column and bitline parasitic capacitance, so its weighted accumulation is temporal and per-column rather than a literal 2D capacitor matrix (Yang et al., 29 May 2026). The passive switched-capacitor matrix multiplier is logically 2D at the algorithm level $C_{\text{tot}}$9, but physically it is a sequentially reused switched-capacitor MAC rather than a simultaneous 2D capacitor fabric (Lee et al., 2016).

A second misconception is that geometry alone fixes capacitance in planar arrays. The 2DEG theory shows that when one or both electrodes are two-dimensional electron systems, the capacitance can substantially exceed geometric expectations because the electronic equation of state modifies the effective thickness $$V_{\text{out}}=\frac{1}{C_{\text{tot}}}\sum_{(i,j)\in\mathcal{A}} C_{ij}V_{\text{ref}}\,b_{ij}.$$0 (Skinner et al., 2010). For arrayed cells, this means that a purely geometric extraction can be inadequate if one electrode is a correlated low-density 2D system (Skinner et al., 2010).

A third misconception is that equivalent series/parallel reduction is sufficient for multi-electrode tunable cells. The capacitor-within-capacitor work explicitly warns that thin gate electrodes do not fully screen polarization and that a capacitance-matrix description is more faithful than lumped cartoons (Grebel, 2017). Similar caveats appear in printed and textile systems, where ESR, leakage, front-end impedance, and distributed RC effects materially alter the usable weighting function (Worsley et al., 2018, Gu et al., 2011).

The design consequences are therefore domain-specific. In charge-domain SRAM-CIM, the dominant issues are capacitor matching, ADC precision, and hybrid partitioning between digital and analog computation (Konno et al., 25 Aug 2025). In spatially distributed or materials-defined arrays, the dominant issues are local constitutive nonlinearity, distributed resistance, parasitic coupling, disorder, and extraction fidelity (Skinner et al., 2010, Gu et al., 2011, Rodriguez et al., 10 Nov 2025). This suggests that “2D-weighted capacitor array” is best treated not as a single canonical object, but as a family of architectures unified by two-dimensional organization of capacitance weights or capacitive response, with the 28 nm hybrid complex SRAM-CIM macro providing the most precise direct definition now in use (Konno et al., 25 Aug 2025).