Switched-Capacitor Charging Mechanism

• Switched-capacitor charging mechanisms are discrete-time processes that use controlled switch sequences to charge, redistribute, and store energy through capacitors.
• The techniques leverage fundamental charge redistribution and canonical switching sequences to achieve precise voltage conversion, offset cancellation, and efficient energy transfer.
• They are applied in diverse regimes including quantum-dot biasing, piezoelectric harvesting, multilevel power inversion, DC-DC conversion, and mixed-signal in-memory computation.

Switched-capacitor charging mechanism denotes a class of discrete-time charge-transfer processes in which capacitors are periodically connected, disconnected, stacked, paralleled, polarity-reversed, or left floating so that voltage storage, voltage conversion, charge inversion, or energy extraction is determined by charge conservation under a prescribed switching sequence. In the cited literature, the same mechanism appears in charge-locking for Si/SiGe quantum dots, binary-resolution switched-capacitor DC-DC conversion, one-stage SSHC rectification, five-level common-ground inversion, piezoelectric harvesting with SECE and a switched-capacitor array, auto-zero amplification, and mixed-signal in-memory GRU computation (Xu et al., 2020, Kushnerov, 2010, Du, 2019, Marahatta et al., 19 Sep 2025, Karmakar et al., 16 Jul 2025, Mishonov et al., 2015, Billaudelle et al., 13 May 2025).

1. Fundamental charge-redistribution principle

At the most elementary level, a switched-capacitor charging mechanism separates charging and redistribution into distinct phases. In the Si/SiGe charge-locking cell, Phase $\phi_1$ charges the sampling capacitor so that $Q_{\rm initial}=C_1\cdot V_{\rm in}$, and Phase $\phi_2$ shares that charge with the holding capacitor, giving a floating-node voltage

$V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$

After the transfer switch is opened, the node is isolated on $C_2$ together with parasitic capacitances, and the stored voltage is retained until refresh (Xu et al., 2020).

The same conservation principle appears in the double-switch capacitor network used for auto-zero and chopper-stabilized amplification. In the DOWN state, $C_1$ is charged to the parasitic offset $E$ while $C_2$ floats. In the UP state, $C_1$ and $C_2$ are placed in series across $Q_{\rm initial}=C_1\cdot V_{\rm in}$0, the intermediate node is floating, and the update law becomes

$Q_{\rm initial}=C_1\cdot V_{\rm in}$1

Its fixed point is $Q_{\rm initial}=C_1\cdot V_{\rm in}$2, so repeated switching cancels the offset contribution and leaves the signal of interest on the measurement capacitor (Mishonov et al., 2015).

A many-way variant appears in switched-capacitor in-memory computation. In MINIMALIST, each synapse capacitor is first sampled to a selected weight voltage during $Q_{\rm initial}=C_1\cdot V_{\rm in}$3, and all capacitors in a column then share onto a common node during $Q_{\rm initial}=C_1\cdot V_{\rm in}$4. In the ideal case, ignoring small $Q_{\rm initial}=C_1\cdot V_{\rm in}$5,

$Q_{\rm initial}=C_1\cdot V_{\rm in}$6

which reduces to an averaged column voltage when $Q_{\rm initial}=C_1\cdot V_{\rm in}$7 (Billaudelle et al., 13 May 2025).

2. Canonical switching sequences

Two-phase operation is the simplest recurrent pattern. Non-overlapping clocks are used to avoid direct feedthrough and unintended conductive overlap. In quantum-dot charge locking, one phase samples the analog bias onto $Q_{\rm initial}=C_1\cdot V_{\rm in}$8, and the other phase transfers it to the holding node. In MINIMALIST, $Q_{\rm initial}=C_1\cdot V_{\rm in}$9 samples the synapse capacitors, $\phi_2$0 performs charge sharing, and a third phase $\phi_2$1 is used only for gated state updates in the recurrent cell (Xu et al., 2020, Billaudelle et al., 13 May 2025).

Three-phase operation is central to one-stage SSHC rectification. The sequence $\phi_2$2 first connects $\phi_2$3 and $\phi_2$4 in parallel with identical polarity, then clears $\phi_2$5 to zero volts while $\phi_2$6 holds charge, and finally reconnects $\phi_2$7 to $\phi_2$8 with reversed polarity. The result is partial inversion of the piezoelectric transducer voltage without an inductor (Du, 2019).

A related but distinct two-interval sequence appears in the SECE-based piezoelectric harvester with a switched-capacitor array. During Phase I, the SECE switch is open, the piezo current charges the rectifier capacitor $\phi_2$9, and the digitally controlled SCA fixes

$V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$0

At each mechanical peak, Phase II closes the SECE switch for a brief interval $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$1, forming an LC resonance between $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$2 and $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$3 and transferring the charge on $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$4 into the storage capacitor in a near-lossless pulse (Karmakar et al., 16 Jul 2025).

Series/parallel reconfiguration is the characteristic pattern in multilevel switched-capacitor power conversion. In the five-level common-ground inverter, $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$5 and $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$6 operate as a flying switched-capacitor cell: they are stacked in series to yield $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$7 or $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$8 for the $V_f=\frac{Q_{\rm initial}}{C_1+C_2}.$9 output levels, and reconfigured in parallel to appear as $C_2$0 for the $C_2$1 levels. A third capacitor $C_2$2 acts as an integrated charge-pump element: it is charged from the H-bridge DC bus during zero or freewheeling states and then connected in parallel with $C_2$3 to refresh their voltage (Marahatta et al., 19 Sep 2025).

3. Governing equations, resolution limits, and nonidealities

The ideal relations $C_2$4 and charge conservation are only the first layer of analysis. In a sample-and-hold floating node, accuracy is limited by random and systematic terms. For the Si/SiGe charge-locking structure, the random resolution limits are

$C_2$5

corresponding respectively to single-electron quantization and $C_2$6 noise. Systematic offsets include channel-charge injection,

$C_2$7

and parasitic gate-source coupling,

$C_2$8

Retention is set by leakage, with

$C_2$9

and the measured droop for device B is approximately $C_1$0 (Xu et al., 2020).

In switched-capacitor DC-DC conversion, the dominant loss is often captured by an equivalent resistance rather than by a static leakage model. Kushnerov’s binary SCC derives

$C_1$1

for a single flying-capacitor topology, and a topology-specific closed form for $C_1$2,

$C_1$3

Here the switched-capacitor charging mechanism is not treated as lossless; it is modeled as a dissipative conversion process whose power loss depends on switching period, capacitance, and series resistance (Kushnerov, 2010).

In one-stage SSHC rectification, the central performance quantity is the single-cycle voltage inversion efficiency

$C_1$4

When $C_1$5, repeated flips converge to an effective inversion of $C_1$6 of the open-circuit peak. In the opposite limit $C_1$7, the residual voltage approaches $C_1$8 after many flips. These results formalize the fact that purely capacitive inversion is partial rather than complete (Du, 2019).

4. Self-adjustment, balancing, and convergence

A notable property of several switched-capacitor charging mechanisms is self-adjustment. In Kushnerov’s extended-binary framework, any fraction

$C_1$9

can be represented as

$E$0

with $E$1 and each $E$2. The redundancy is not incidental: every $E$3 has at least $E$4 distinct EXB codes, and every $E$5 in one code forces at least one $E$6 in the same bit-position of another code, ensuring that each flying capacitor is both charged and discharged over a full cycle. The resulting KVL and charge-conservation system has a unique solution, so the capacitor voltages self-adjust to exact binary-weighted levels regardless of initial conditions (Kushnerov, 2010).

Self-balancing also appears in the five-level common-ground inverter. The topology alternates $E$7 and $E$8 between series use for the $E$9 states and parallel use for the $C_2$0 states, with the timing intervals $C_2$1 and $C_2$2 held equal in magnitude each half-cycle. The paper states that no active voltage sensing or extra control loops are required, because the series/parallel alternation itself enforces equal voltages on the switched-capacitor cell (Marahatta et al., 19 Sep 2025).

Convergence by repeated switching is equally explicit in auto-zero amplification. The recurrence

$C_2$3

has fixed point $C_2$4, and after $C_2$5 cycles the residual offset decays as $C_2$6. The mechanism therefore acts as an iterative offset-cancellation process rather than as a single-shot subtraction (Mishonov et al., 2015).

In cryogenic quantum-dot charge locking, the corresponding long-time property is retention rather than algebraic self-balancing. Leakage in cryogenic operation is described as extremely low, enabling retention for seconds to minutes without refresh. This suggests that the switched-capacitor cell can serve not merely as a transient sampler but as a local analog memory element for static gate biasing (Xu et al., 2020).

5. Major application regimes

Quantum-dot control: In the Si/SiGe implementation, parallel-plate capacitors, transistors, and quantum-dot devices are monolithically fabricated on a Si/SiGe-based substrate. The bottom plate of the holding capacitor is formed by a heavily implanted reservoir and spans the $C_2$7 to $C_2$8 range; the dielectric is $C_2$9 ALD Al$C_1$0O$C_1$1; and the FET channel is the Si quantum well itself. The electrochemical potential of the dot can follow a $C_1$2 pulse signal while the plunger gate is partially floating, and the dynamic test shows two distinct Coulomb-peak patterns at $C_1$3 and $C_1$4 under a $C_1$5 square wave on a neighboring gate (Xu et al., 2020).

Piezoelectric harvesting with adaptive tuning: The simulated PEH front end combines a nonlinear piezo model, SECE, Hybrid MPPT, and a digitally controlled switched-capacitor array consisting of five binary-weighted capacitors $C_1$6. At a fixed $C_1$7 drive, the complete SECE + SCA + Hybrid-MPPT system delivers about $C_1$8 to a $C_1$9 load; the MPPT loop operates at $C_2$0–$C_2$1 efficiency; and when ambient frequency drifts from $C_2$2 to $C_2$3, the SCA-tuned system harvests up to $C_2$4 more power than a baseline SECE-only harvester. The usable bandwidth is extended by $C_2$5 around the nominal resonance (Karmakar et al., 16 Jul 2025).

Multilevel power inversion: In the five-level common-ground inverter for transformerless residential PV, the switched-capacitor network maintains $C_2$6 and $C_2$7 within $C_2$8 of their nominal value throughout the sine cycle, reaches $C_2$9 peak efficiency at rated $Q_{\rm initial}=C_1\cdot V_{\rm in}$00, and reports unfiltered waveform THD of $Q_{\rm initial}=C_1\cdot V_{\rm in}$01. On a step load from $Q_{\rm initial}=C_1\cdot V_{\rm in}$02 to $Q_{\rm initial}=C_1\cdot V_{\rm in}$03, the output voltage is held within $Q_{\rm initial}=C_1\cdot V_{\rm in}$04 of $Q_{\rm initial}=C_1\cdot V_{\rm in}$05 (rms), and the design achieves a greater than $Q_{\rm initial}=C_1\cdot V_{\rm in}$06 reduction in total DC-link capacitance while maintaining stable capacitor voltages during $Q_{\rm initial}=C_1\cdot V_{\rm in}$07, $Q_{\rm initial}=C_1\cdot V_{\rm in}$08, and $Q_{\rm initial}=C_1\cdot V_{\rm in}$09 voltage sags (Marahatta et al., 19 Sep 2025).

Binary-resolution DC-DC conversion: In the self-adjusting SCC, the no-load conversion ratio is

$Q_{\rm initial}=C_1\cdot V_{\rm in}$10

and adding capacitors increases the number of target ratios to as many as $Q_{\rm initial}=C_1\cdot V_{\rm in}$11. For the $Q_{\rm initial}=C_1\cdot V_{\rm in}$12 experimental system, simulation and experiment show peak efficiencies greater than $Q_{\rm initial}=C_1\cdot V_{\rm in}$13 at each $Q_{\rm initial}=C_1\cdot V_{\rm in}$14, average efficiencies greater than $Q_{\rm initial}=C_1\cdot V_{\rm in}$15 from $Q_{\rm initial}=C_1\cdot V_{\rm in}$16 to $Q_{\rm initial}=C_1\cdot V_{\rm in}$17 input, and output ripple below $Q_{\rm initial}=C_1\cdot V_{\rm in}$18 in hardware (Kushnerov, 2010).

Mixed-signal in-memory computation: MINIMALIST uses switched-capacitor circuits not only for in-memory computation but also for gated state updates in minimal GRUs. The core relies on metal-insulator-metal capacitors, CMOS transmission gates, $Q_{\rm initial}=C_1\cdot V_{\rm in}$19 SRAM cells, and a single SAR ADC per column. The update gate $Q_{\rm initial}=C_1\cdot V_{\rm in}$20 is digitized at $Q_{\rm initial}=C_1\cdot V_{\rm in}$21, and the recurrent state update is implemented by swapping a programmable fraction $Q_{\rm initial}=C_1\cdot V_{\rm in}$22 of capacitor banks so that

$Q_{\rm initial}=C_1\cdot V_{\rm in}$23

The same charge-sharing formalism is therefore used for both matrix-vector accumulation and state interpolation (Billaudelle et al., 13 May 2025).

Precision amplification: In the Goldberg-Lehmann double-switch topology, repeated charging and reconnection drive the measurement capacitor toward the true signal $Q_{\rm initial}=C_1\cdot V_{\rm in}$24 while suppressing the parasitic offset. The historical role of this mechanism is explicit: modern auto-zero amplifiers sample the offset on on-chip capacitors and subtract it on the next half-cycle, while chopper amplifiers modulate and demodulate to suppress low-frequency offset and $Q_{\rm initial}=C_1\cdot V_{\rm in}$25 noise (Mishonov et al., 2015).

6. Design trade-offs, limitations, and common misconceptions

Capacitor sizing improves some figures of merit while degrading others. In the quantum-dot charge-locking cell, increasing $Q_{\rm initial}=C_1\cdot V_{\rm in}$26 improves voltage resolution through $Q_{\rm initial}=C_1\cdot V_{\rm in}$27, reduces thermal noise as $Q_{\rm initial}=C_1\cdot V_{\rm in}$28, and reduces systematic $Q_{\rm initial}=C_1\cdot V_{\rm in}$29 and $Q_{\rm initial}=C_1\cdot V_{\rm in}$30 roughly as $Q_{\rm initial}=C_1\cdot V_{\rm in}$31. The same increase, however, consumes die area and increases refresh power according to

$Q_{\rm initial}=C_1\cdot V_{\rm in}$32

if frequent refresh is needed. Reducing the transistor size lowers $Q_{\rm initial}=C_1\cdot V_{\rm in}$33 and $Q_{\rm initial}=C_1\cdot V_{\rm in}$34 and reduces switching power,

$Q_{\rm initial}=C_1\cdot V_{\rm in}$35

but very short or narrow channels raise $Q_{\rm initial}=C_1\cdot V_{\rm in}$36, slow switching, and may increase hysteresis. The same study states that sub-$Q_{\rm initial}=C_1\cdot V_{\rm in}$37 resolution at $Q_{\rm initial}=C_1\cdot V_{\rm in}$38 requires $Q_{\rm initial}=C_1\cdot V_{\rm in}$39, while keeping systematic offsets below $Q_{\rm initial}=C_1\cdot V_{\rm in}$40 requires $Q_{\rm initial}=C_1\cdot V_{\rm in}$41 and $Q_{\rm initial}=C_1\cdot V_{\rm in}$42 (Xu et al., 2020).

A second trade-off concerns inversion or balancing efficiency versus physical size. In one-stage SSHC, choosing $Q_{\rm initial}=C_1\cdot V_{\rm in}$43 gives quick convergence to the $Q_{\rm initial}=C_1\cdot V_{\rm in}$44 limit, whereas approaching $Q_{\rm initial}=C_1\cdot V_{\rm in}$45 requires $Q_{\rm initial}=C_1\cdot V_{\rm in}$46, which in turn implies a physically large off-chip capacitor and slower build-up over many cycles. The paper reports a diminishing return above approximately $Q_{\rm initial}=C_1\cdot V_{\rm in}$47, and it notes that series resistance, switch on-resistance, diode drops, finite switching times, and leakage all reduce the practical flip ratio below the ideal $Q_{\rm initial}=C_1\cdot V_{\rm in}$48 (Du, 2019).

A third trade-off is combinatorial. In binary-resolution SCCs, increasing bit-count produces more closely spaced target ratios and therefore reduces the spacing between adjacent no-load conversion levels to $Q_{\rm initial}=C_1\cdot V_{\rm in}$49. This supports high efficiency over a wide input-voltage range, but it also increases the number of flying capacitors and switching topologies. The minimum number of topologies is $Q_{\rm initial}=C_1\cdot V_{\rm in}$50, and further design work is needed to eliminate redundant topologies and reduce $Q_{\rm initial}=C_1\cdot V_{\rm in}$51 (Kushnerov, 2010).

Two recurring misconceptions are corrected by the literature. First, switched-capacitor charging is not restricted to step-up charge pumping or conventional DC-DC conversion; it also functions as local analog storage, offset cancellation, charge inversion, adaptive impedance tuning, and mixed-signal vector accumulation. Second, larger capacitance is not universally preferable. The reported area, power, volume, settling-time, and topology-count penalties show that capacitor choice is a constrained optimization across accuracy, retention, ripple, efficiency, and integration density. A plausible implication is that the decisive design question is not simply how much capacitance to add, but where in the switching sequence that capacitance should be sampled, shared, isolated, or refreshed.