Quantinuum H1-1 and H2-1 two-qubit gate times unknown

Ascertain the native two-qubit gate times for the Quantinuum H1-1 and Quantinuum H2-1 trapped-ion quantum processors, which were unavailable in the vendor documentation used in this study, to enable accurate execution-time estimates and fair cross-platform comparisons for LR-QAOA circuits.

Background

The LR-QAOA benchmarking protocol compares performance across diverse quantum processing units, and accurate characterization of native two-qubit gate times is essential for estimating circuit execution time and depth. The paper compiles device properties from vendor sources to contextualize results.

For Quantinuum H1-1 and H2-1, the authors could not obtain the two-qubit gate times, which complicates precise timing projections and necessitates approximations elsewhere in the manuscript (e.g., using IonQ Aria timings for estimates). Establishing these timings would improve the reliability of timing-based analyses and cross-platform comparisons.