Robustness of post-selected gadget advantage under independently improving hardware parameters

Determine whether the post-selected fan-out gadget compilation for product-formula simulation of Heisenberg-type spin Hamiltonians continues to outperform the sequential compilation when two-qubit gate error rates and qubit coherence times improve at different rates.

Background

The numerical noise study scales gate-error probabilities and coherence times by the same factor, thereby exploring only a one-parameter trajectory in which gate fidelity and coherence improve proportionally. The post-selected gadget benefits from reduced depth, which lowers exposure to idle relaxation, but its redundant registers increase the exposure to phase-flip-induced logical dephasing during interaction windows. Consequently, its relative performance may depend on whether gate errors and coherence times improve in different proportions. The paper explicitly leaves this robustness question unresolved.

References

The demonstration therefore locates the crossover along a single trajectory of jointly improving gate fidelity and coherence; whether the post-selected gadget still leads when the two improve at different rates is left to future work.

— Logarithmic depth compression of Heisenberg Hamiltonian simulation by fan-out parallelization, with built-in error detection  (2608.20250 - Burov et al., 20 Aug 2026) in Appendix A, Section “Noise model”