Rigorous methodology linking component-level and system-level benchmarks

Establish a rigorous methodology that quantitatively connects component-level error metrics—such as average single-qubit and two-qubit gate infidelities, state-preparation-and-measurement errors, mid-circuit measurement-and-reset crosstalk, and transport-induced memory errors—to system-level performance measures, including per-layer process fidelities in random Clifford circuits with mid-circuit measurements on trapped-ion QCCD processors like Helios. The methodology should enable principled, non-heuristic comparison between predictions derived from component-level benchmarks and observed outcomes in system-level volumetric benchmarks (e.g., binary randomized benchmarking with mid-circuit measurements).

Background

In the system-level paper using random Clifford circuits with mid-circuit measurements, the authors infer effective error parameters (e.g., effective two-qubit gate error and effective MCMR error) from layer fidelities and compare them to predictions based on independently measured component-level benchmarks. This comparison currently relies on heuristic gate-counting and simplified error aggregation.

While the effective two-qubit error derived from system-level data is broadly consistent with component-level measurements, the methodology lacks a rigorous, general framework to translate detailed component-level error channels (including leakage, crosstalk, and memory effects) into accurate system-level fidelity predictions that account for circuit structure, parallel scheduling, and runtime compilation. The authors explicitly identify the absence of such a rigorous methodology as an open problem.