Optimize hardware designs of superconducting erasure qubits

Investigate and develop modifications to the physical designs of dual-rail encoded superconducting erasure qubits to further optimize the advantage gained from engineered erasure-biased noise, and quantitatively assess the impact of these design changes on thresholds, logical error rates, and infrastructure complexity when concatenated with an outer code.

Background

The paper discusses several superconducting implementations of erasure qubits—coupled transmons, multimode (dimon) qubits, and cavity QED systems—each achieving heralded erasures with distinct coherence and control trade-offs. Alternative designs (e.g., qutrit-based encodings or fluxonium molecules) are also proposed, suggesting a broad design space.

Since erasure-biased noise can raise thresholds and reduce logical error rates without dramatically increasing control complexity, optimizing device architectures (including erasure checks, reset protocols, and coupling schemes) is a key opportunity. A concrete research direction is to refine hardware features to maximize erasure dominance while minimizing residual Pauli errors and leakage, maintaining scalability and compatibility with outer-code decoding.