General Framework for Selecting Reduced Instruction Sets

Determine whether a general framework can be established to optimize the selection of reduced instruction sets for superconducting quantum processors by balancing calibration costs and compilation efficiency across applications, and, if so, specify the principles and procedures that such a framework should employ.

Background

Superconducting quantum processors require extensive calibration of gate implementations; reducing the instruction set can lower calibration overhead but may impact compilation efficiency and algorithm performance. The trade-offs are application-dependent today, and the authors highlight the lack of a unifying methodology.

Establishing a general framework would guide hardware–software co-optimization by quantifying calibration cost versus compiler efficiency, potentially enabling more scalable operation and easier maintenance of large systems.

References

Optimizing selection of reduced instruction sets, by balancing trade-offs between calibration costs and compilation efficiency is also an opportunity, where the analysis of these trade-offs is application-specific and the possibility of a general framework remains an open question.

— Enabling Technologies for Scalable Superconducting Quantum Computing (2512.15001 - Croot et al., 17 Dec 2025) in Section 'QPU Tune-up and Operation' → Subsection 'QPU Pulse-design, Tune-Up and Calibration' → Bullet list 'Some other outstanding challenges include:'