Optimized Hardware Kernels for Ternary Operations

Develop and evaluate optimized hardware kernels for ternary operations to efficiently support training and inference of 1.58-bit quantized architectures such as Hybrid Gated Flow (HGF).

Background

HGF relies on a ternary weight backbone for efficiency, with theoretical speedups contingent on specialized support for ternary arithmetic. The paper notes that realizing full speedup requires optimized kernels beyond standard CUDA paths.

Although the authors report custom Triton kernels under development, they explicitly list hardware kernel optimization for ternary operations as an open question, underscoring the gap between theoretical and practical performance.

References

Key open questions include: (1) scaling behavior to billion-parameter models, (2) hardware kernel optimization for ternary operations, (3) adaptive gating mechanisms that vary across layers or heads, and (4) application to other modalities (vision, audio).

— Hybrid Gated Flow (HGF): Stabilizing 1.58-bit LLMs via Selective Low-Rank Correction  (2602.05269 - Pizzo, 5 Feb 2026) in Conclusion, Future Directions

The result is a validated scale-up baseline: model size improves robustness to aggressive post-training discretization, actual serialization is solved for the measured artifact, and direct execution is feasible, while broader seeds, calibration distributions and kernel optimization remain open.

— Scaling Post-Training Ternarisation to Qwen3-8B Capability Retention, Reproduction, Lossless Packing, and Packed Execution  (2609.09240 - Malik et al., 8 Sep 2026) in Abstract

The central systems lesson is therefore explicit: compression is demonstrated; deployment acceleration remains an open engineering problem.

— Post-Training Ternarization of Qwen3-4B Capability, Effective Bit Budget, Storage Compression, and Deployment  (2609.01962 - Malik et al., 2 Sep 2026) in Executive takeaway; discussed further in Sections 10, 12, and the Conclusion