Optimized Hardware Kernels for Ternary Operations

Develop and evaluate optimized hardware kernels for ternary operations to efficiently support training and inference of 1.58-bit quantized architectures such as Hybrid Gated Flow (HGF).

Background

HGF relies on a ternary weight backbone for efficiency, with theoretical speedups contingent on specialized support for ternary arithmetic. The paper notes that realizing full speedup requires optimized kernels beyond standard CUDA paths.

Although the authors report custom Triton kernels under development, they explicitly list hardware kernel optimization for ternary operations as an open question, underscoring the gap between theoretical and practical performance.