Efficient implementation of three-factor spike-based learning on hybrid CMOS/memristive hardware

Develop efficient hardware implementations of three-factor spike-based learning rules, including long-lasting eligibility traces, on hybrid CMOS/memristive architectures to enable practical on-chip learning.

Background

Three-factor learning rules, which combine local synaptic activity with modulatory signals, can approximate backpropagation and solve temporal credit assignment. Implementing these rules at scale requires synaptic eligibility traces and energy-efficient memory mechanisms.

The thesis introduces PCM-trace as a building block but identifies the broader challenge of efficient end-to-end realization of these rules on mixed-signal hardware with memristive devices.