Trapped-ion QCCD: Modular Ion-Trap Architecture

Updated 5 July 2026

Trapped-ion QCCD is a modular architecture that partitions ions across specialized trap zones to achieve targeted high-fidelity quantum operations.
The system employs precise waveform synthesis and convex electrode-voltage optimization to minimize motional excitation during ion shuttling.
It addresses scaling challenges by optimizing trap capacity, cooling protocols, and dynamic routing to enhance overall quantum processor performance.

Searching arXiv for recent and foundational QCCD papers relevant to trapped-ion QCCD and electrode-control hardware. The trapped-ion Quantum Charge-Coupled Device (QCCD) is a modular ion-trap architecture in which quantum information is stored in ions distributed across multiple trapping zones and communicated by physically transporting those ions between memory, gate, readout, cooling, and auxiliary regions using time-dependent electrode voltages. In contrast to a single long ion chain, QCCD aims to preserve high-fidelity local operations in small crystals while recovering effective all-to-all connectivity through shuttling, split/merge operations, and junction crossings. This architectural program spans microfabricated trap design, transport waveform synthesis, compiler and scheduler design, and system-level benchmarking, with recent work emphasizing high-voltage control hardware as a direct enabler of faster, lower-heating transport (Murali et al., 2020, Oshio et al., 2024).

1. Architectural concept and physical organization

QCCD partitions a trapped-ion processor into multiple zones or traps connected by transport links. In one architectural study, the full quantum computer is built from many small ion traps, each holding a modest number of ions, typically 10–30; within one trap, the ions form a linear chain, and high-fidelity single- and two-qubit gates are executed by laser pulses on co-located qubits, while distant qubits are linked by physically transporting ions between traps via segmented electrodes and junctions (Murali et al., 2020). A related graph abstraction distinguishes memory zones $M$ , processing zones $P$ , junctions $J$ , and shuttle channels $S$ , with the composite layout represented as an undirected graph $G=(V,E)$ whose major nodes correspond to junctions and minor nodes to sites between junctions (Schoenberger et al., 2024).

This modular decomposition is not unique. Multi-zone compiler models separate a shielded, two-dimensional grid-type Memory Zone from multiple Processing Zones connected through Y-junction entry and exit paths, explicitly imposing capacity constraints and internal linear routing constraints on each processing zone (Schoenberger et al., 12 May 2025). Hardware realizations likewise vary: the 2020 Honeywell surface-trap demonstration used sixteen functional zones, including two gate zones, two extended-gate zones, two load/auxiliary zones, and ten storage zones, with 198 independent DC electrodes and a cryogenic surface-electrode implementation (Pino et al., 2020). Later systems introduced alternative geometries, including a race-track layout with periodic boundary conditions (Moses et al., 2023) and a rotatable ion storage ring coupled through an X-junction to quantum operation regions in a 98-qubit processor (Ransford et al., 7 Nov 2025).

The architectural rationale is consistent across these variants. By keeping ion count per local crystal limited, QCCD preserves favorable motional spectra and gate conditions inside a zone, while transport restores connectivity at the system level. This suggests that QCCD is best understood not as a single device layout, but as a family of modular trapped-ion organizations defined by zone specialization, transport primitives, and controller-mediated reconfiguration.

2. Transport primitives, confinement, and motional constraints

QCCD operation depends on a small set of transport primitives. A shuttling operation typically consists of splitting the source chain into two subchains, moving one subchain or a single ion along a series of trap segments and junctions, and merging the incoming ions into the destination chain (Murali et al., 2020). The Honeywell demonstration reported low-heating realizations of several such primitives, summarized below (Pino et al., 2020).

Operation	Duration $(\mu\text{s})$	Motional excitation
Intrazone shift $(110\,\mu\text{m})$	58	axial $<1$ , radial $<0.5$
Interzone shift $(\mathrm{G1}\leftrightarrow \mathrm{G2})$	283	axial $P$ 0, radial $P$ 1
Split/Combine of $P$ 2 ions	128	axial $P$ 3, radial $P$ 4
Swap $P$ 5	200	axial $P$ 6, radial $P$ 7

The central physical constraint is motional excitation. For QCCD shuttling to remain compatible with high-fidelity entangling gates, transport must be nearly adiabatic. One recent hardware study states this explicitly as $P$ 8, where $P$ 9 is transport speed, $J$ 0 the transport distance, and $J$ 1 the axial secular frequency; higher secular frequencies therefore permit faster adiabatic shuttling with minimal motional excitation (Oshio et al., 2024). In the same source, the axial secular frequency in a linear Paul trap or segmented surface trap is written, to leading order, as

$J$ 2

with $J$ 3, implying

$J$ 4

This scaling links transport quality directly to available control-voltage headroom. If all electrode voltages are increased by a factor $J$ 5, then $J$ 6 (Oshio et al., 2024). The implication is operational rather than merely formal: faster transport is not only a question of better scheduling, but also of generating larger, low-noise, rapidly updated waveforms while maintaining trap curvature.

The time-dependent trapping problem is commonly expressed through harmonic transport Hamiltonians. During transport, one system-level experiment modeled ion motion along the transport axis as

$J$ 7

with $J$ 8 determined by the voltage waveform; smooth $J$ 9 ramps were used to suppress motional excitation (Pino et al., 2020). This establishes the characteristic QCCD synthesis problem: one must simultaneously control trajectory, curvature, and bandwidth.

3. Control electronics and voltage synthesis

The recent development of a bipolar $S$ 0 V FPGA-based digital-to-analog converter system addresses a specific bottleneck in QCCD transport control. The hardware uses an AMD Zynq-7020 SoC on a Digilent ZedBoard, sixteen channels of AD3542R dual 16-bit DACs with $S$ 1 V native outputs, and non-inverting ADA4700 amplifier stages with gain $S$ 2 to realize $S$ 3 V full scale (Oshio et al., 2024). Reported figures are a maximum update rate of 16 mega-updates per second per channel, slew rate of $S$ 4, analog bandwidth $S$ 5 kHz, and 16-bit resolution over $S$ 6 V, corresponding to $S$ 7 mV LSB; firmware stores waveforms in on-chip BRAM, uses a “chunk sequencer” in FPGA fabric to read sample buffers at 16 MHz, and streams new patterns from the ARM processor via SPI (Oshio et al., 2024).

The same work formulates waveform generation as a convex quadratic program over the electrode-voltage vector $S$ 8:

$S$ 9

subject to

$G=(V,E)$ 0

where $G=(V,E)$ 1 collects the five unique electrode voltages, $G=(V,E)$ 2, $G=(V,E)$ 3, and $G=(V,E)$ 4 impose box constraints $G=(V,E)$ 5 with $G=(V,E)$ 6 V or 10 V in comparison runs (Oshio et al., 2024). Using this approach, the authors reported static secular-frequency measurements of $G=(V,E)$ 7 kHz under a $G=(V,E)$ 8 V DAC limit and $G=(V,E)$ 9 kHz with the $(\mu\text{s})$ 0 V system, matching the expected $(\mu\text{s})$ 1 scaling from $(\mu\text{s})$ 2 (Oshio et al., 2024). They also reported 200 $(\mu\text{s})$ 3m transport in 10 steps $(\mu\text{s})$ 4s $(\mu\text{s})$ 5 ms round trip, repeated 10,000 times with no ion loss under continuous Doppler cooling, and negligible motional excitation at these speeds when $(\mu\text{s})$ 6 kHz (Oshio et al., 2024).

At larger scale, direct one-DAC-per-electrode control becomes a systems problem. A time-division-multiplexed architecture replaces dedicated DACs by a high-speed DAC, a demultiplexer or switch bank, sample-and-hold capacitors, and buffer amplifiers. In the resource analysis of one study, a QCCD trapped-ion quantum computer with 10,000 trap electrodes can be controlled using only 13 field-programmable gate arrays and 104 high-speed DACs, rather than 10,000 dedicated DACs (Ohira et al., 2 Apr 2025). The key scaling relations are

$(\mu\text{s})$ 7

with a worked example using $(\mu\text{s})$ 8 MHz, $(\mu\text{s})$ 9 MSps, and $(110\,\mu\text{m})$ 0, yielding $(110\,\mu\text{m})$ 1 and, in practice, 104 DACs across 13 FPGAs (Ohira et al., 2 Apr 2025). This places electrode-control architecture alongside trap design and compiler strategy as a first-order determinant of QCCD scalability.

Integrated photonics introduces a complementary control direction. In a photonics-enabled surface-electrode QCCD device, transport of an ion over 375 $(110\,\mu\text{m})$ 2m in 200 $(110\,\mu\text{m})$ 3s was combined with coherent multi-zone operations; dielectric charging from exposed photonic windows was compensated by “fictitious coupler voltages,” reducing coherent excitation from $(110\,\mu\text{m})$ 4 quanta and $(110\,\mu\text{m})$ 5 quanta per shuttle to $(110\,\mu\text{m})$ 6 quanta and $(110\,\mu\text{m})$ 7 (Mordini et al., 2024). This indicates that voltage synthesis in QCCD is increasingly coupled to non-electrical integration technologies rather than being confined to conventional trap-electrode optimization.

4. Compilation, routing, and schedule synthesis

Because QCCD connectivity is realized dynamically, compilation is inseparable from physical transport. One end-to-end architectural toolflow takes architecture parameters, application workloads, and hardware performance models as input; applies greedy qubit mapping and dependency-respecting gate scheduling; inserts split, move, merge, and chain-reordering operations; and simulates execution to compute runtime, reliability, and device noise rates (Murali et al., 2020). Its shuttling latency model is

$(110\,\mu\text{m})$ 8

with representative values $(110\,\mu\text{m})$ 9s, $<1$ 0s, $<1$ 1s/segment, $<1$ 2s, and $<1$ 3s (Murali et al., 2020). The corresponding gate-fidelity model is

$<1$ 4

with application-level fidelity

$<1$ 5

or, in the same study’s simplified notation,

$<1$ 6

treating shuttles as identity while accounting for their heating in $<1$ 7 (Murali et al., 2020). Quantitatively, that study reported that trap sizing and communication topology can affect application reliability by up to three orders of magnitude, while microarchitectural gate-implementation choices contribute another order of magnitude (Murali et al., 2020).

Subsequent work has focused on more exact or more hardware-explicit formulations. A heuristic shuttling scheduler based on dependency-graph front layers and cycle-based path generation produced schedules within $<1$ 8 of the optimal makespan for grids up to $<1$ 9, and exact lower bounds have been obtained by a Boolean satisfiability encoding of memory-zone transport, establishing minimal time-step counts for the first time on benchmark instances (Schoenberger et al., 2024, Schoenberger et al., 2023). Multi-zone orchestration has also moved beyond black-box processing zones: one compiler explicitly models processing-zone capacities, one-way Y-junction entry and exit paths, and the inability of ions to bypass one another inside a linear processing zone, then combines qubit partitioning via repeated bisection of an interaction graph with dependency-aware gate selection (Schoenberger et al., 12 May 2025). On reported benchmarks, dependency-aware gate selection reduced total execution time by 52–88% compared to naively walking the circuit gate by gate, and adding multiple processing zones yielded a further 30–60% speedup over a single-processing-zone baseline (Schoenberger et al., 12 May 2025).

More recent routing work has made the shuttle/SWAP trade-off explicit. S-SYNC introduces a weighted static-topology formulation in which QCCD physical operations are cast as “generic swaps” on a graph, reporting an average 3.69x reduction in shuttling and a 1.73x improvement in application success rate relative to prior baselines (Zhu et al., 2 May 2025). A later adaptive routing strategy adds a parallelism reward term to the scoring function

$<0.5$ 0

thereby balancing movement overhead against concurrent execution across traps; on an $<0.5$ 1-ion linear topology, it reported large reductions in shuttles and SWAPs together with fidelity improvements across several benchmarks (Ovide et al., 20 Mar 2026). These developments indicate that QCCD compilation is no longer accurately described as routing alone: it is a co-optimization problem over placement, transport, parallelism, and local chain organization.

5. Experimental realizations and system-level validation

A full-system QCCD realization was demonstrated in 2020 on a Honeywell cryogenic surface trap, integrating segmented 2D trapping, high-speed low-heating transport primitives, parallel optical delivery, mid-circuit measurement, and programmable circuit execution (Pino et al., 2020). The system used a planar two-layer metal structure on sapphire, RF rails 75 $<0.5$ 2m wide separated by 180 $<0.5$ 3m, a 190 V, 42.35 MHz RF drive, and 198 independent DC electrodes. Reported qubit performance included SPAM error $<0.5$ 4, simultaneous single-qubit gate error $<0.5$ 5, two-qubit gate error $<0.5$ 6, and qubit spin-echo $<0.5$ 7 s (Pino et al., 2020). System-level benchmarks included a teleported CNOT gate using mid-circuit measurement and a quantum volume of $<0.5$ 8 (Pino et al., 2020).

Later QCCD hardware expanded both scale and topology. The H2 race-track processor introduced a linear trap with periodic boundary conditions, electrode broadcasting, and multi-layer RF routing, initially operating with 32 qubits and reporting average SPAM error $<0.5$ 9, average single-qubit gate infidelity $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 0, and average two-qubit gate infidelity $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 1 (Moses et al., 2023). Its system-level demonstrations included mirror benchmarking, linear cross-entropy benchmarking, $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 2, and preparation of a 32-qubit GHZ state with measured fidelity $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 3 for a log-depth circuit and $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 4 for a constant-depth adaptive circuit (Moses et al., 2023).

The 98-qubit Helios processor extends the QCCD model further by combining a rotatable ion storage ring, an X-junction, a cache, and sixteen quantum operation zones. Averaged over all operational zones, it reported average infidelities of $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 5 for single-qubit gates, $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 6 for two-qubit gates, and $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 7 for state preparation and measurement (Ransford et al., 7 Nov 2025). Its logical connectivity is mediated by dynamic routing through the ring and junction, while program layers proceed by extracting ion pairs, staging them in the cache, loading quantum operation zones, performing logic and cooling, and returning processed qubits to storage (Ransford et al., 7 Nov 2025). A simplified layer-time decomposition for random Clifford layers on all 98 qubits is $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 8 ms, broken down as $(\mathrm{G1}\leftrightarrow \mathrm{G2})$ 9 ms ring rotation, $P$ 00 ms shift, $P$ 01 ms cooling, and $P$ 02 ms logic (Ransford et al., 7 Nov 2025).

These experiments establish that QCCD has progressed from an architectural proposal to a class of functioning processors with system-level benchmarks. They also show that transport is no longer an isolated primitive; it is embedded in complete programming stacks supporting mid-circuit measurement, qubit reuse, and large-scale scheduling.

6. Scaling directions, trade-offs, and unresolved design choices

QCCD scaling is constrained by a set of interdependent trade-offs rather than a single limiting mechanism. One prominent example is trap capacity. For 50–100-qubit NISQ-era studies, a “sweet spot” around $P$ 03 ions per trap was reported, balancing reduced shuttling against slower, noisier intra-trap gates in larger chains (Murali et al., 2020). By contrast, a later surface-code study found that traps of capacity $P$ 04 minimize QEC cycle time and logical error across code distances and gate-fidelity scenarios, with a $P$ 05 grid exhibiting essentially constant $P$ 06 ms per round and outperforming larger traps in logical clock speed and logical error rate (Jones et al., 27 Oct 2025). This is not a contradiction in the narrow sense; it reflects different optimization targets, with application-level NISQ execution and surface-code QEC favoring different operating points.

Topology is similarly workload dependent. A 2D grid can restore three orders of magnitude in reliability for communication-heavy circuits such as Grover and QFT, whereas nearest-neighbor or hardware-efficient workloads can perform just as well on a linear chain (Murali et al., 2020). Ring topologies modestly outperform linear ones on some workloads, while routing heuristics tailored to higher-connectivity layouts remain an open area (Ovide et al., 2024). Parallelism is not automatically beneficial: one study reported that when the ion-move rate exceeds approximately 20% per time step, parallel execution fidelity drops below a single-trap sequential baseline, whereas lower movement rates allow depth reduction to outweigh movement penalties (Ovide et al., 6 Feb 2025).

Cooling remains a major systems issue. In the 2020 Honeywell QCCD, sympathetic cooling time of roughly 1.5 ms per split/transport was identified as a bottleneck (Pino et al., 2020). Exchange cooling offers a different approach: in a single-species protocol using two $P$ 07 ions, the necessary transport and energy exchange were executed in 107 $P$ 08s, removing over 96% and as many as 102(5) quanta of axial motional energy, with negligible added decoherence to the computational ion during re-cooling of the coolant ion (Fallek et al., 2023). A plausible implication is that cooling architecture, no less than gate fidelity, may determine practical QCCD duty cycle.

Microfabrication and junction engineering are also active frontiers. A 3D-printed micro-junction array study reported an X-junction unit cell with $P$ 09 footprint, $P$ 10 higher secular frequency in the linear region relative to a planar trap at the same $P$ 11, $P$ 12 deeper trap depth, and a residual junction barrier $P$ 13 meV, described as approximately a 90% reduction relative to previous surface designs (Taniguchi et al., 21 Sep 2025). Using an RF-noise model, the same work estimated peak $P$ 14 quanta/s at the barrier and round-trip motional excitation $P$ 15 quanta per round trip at $P$ 16 m/s (Taniguchi et al., 21 Sep 2025). These results suggest that junction design is becoming an independent performance lever rather than a fixed geometric constraint.

At the control-system level, direct wiring and time-multiplexed control present another unresolved trade-off. The surface-code architecture study found that standard one-DAC-per-electrode wiring minimizes QEC cycle time but drives data rate and power to very large values, whereas WISE-style multiplexing lowers power by two orders of magnitude but can slow cycle time by up to $P$ 17 because only one transport primitive type can run at once (Jones et al., 27 Oct 2025). Recent $P$ 18 V DAC development and large-scale TDM analyses therefore address not merely convenience, but a core architectural question: whether QCCD scalability will be limited first by motional physics, compiler quality, or electrode-control infrastructure (Oshio et al., 2024, Ohira et al., 2 Apr 2025).

Taken together, these results frame trapped-ion QCCD as a co-designed architecture. Transport fidelity, secular-frequency headroom, junction geometry, compiler heuristics, trap capacity, cooling protocol, topology, and control-electronics scaling all enter materially into the realized performance envelope. The current literature therefore treats QCCD less as a fixed blueprint than as a systems architecture whose optimal form depends on workload regime, error model, and hardware integration path.