A Race Track Trapped-Ion Quantum Processor (2305.03828v2)

Abstract: We describe and benchmark a new quantum charge-coupled device (QCCD) trapped-ion quantum computer based on a linear trap with periodic boundary conditions, which resembles a race track. The new system successfully incorporates several technologies crucial to future scalability, including electrode broadcasting, multi-layer RF routing, and magneto-optical trap (MOT) loading, while maintaining, and in some cases exceeding, the gate fidelities of previous QCCD systems. The system is initially operated with 32 qubits, but future upgrades will allow for more. We benchmark the performance of primitive operations, including an average state preparation and measurement error of 1.6(1)$\times 10^{-3}$, an average single-qubit gate infidelity of $2.5(3)\times 10^{-5}$, and an average two-qubit gate infidelity of $1.84(5)\times 10^{-3}$. The system-level performance of the quantum processor is assessed with mirror benchmarking, linear cross-entropy benchmarking, a quantum volume measurement of $\mathrm{QV}=2^{16}$, and the creation of 32-qubit entanglement in a GHZ state. We also tested application benchmarks including Hamiltonian simulation, QAOA, error correction on a repetition code, and dynamics simulations using qubit reuse. We also discuss future upgrades to the new system aimed at adding more qubits and capabilities.

• The paper introduces its main contribution of a race track trap design that simplifies control through electrode broadcasting and multi-layer RF routing.
• It demonstrates high operational fidelity with a 1Q gate infidelity of 2.5e-5 and successful generation of 32-qubit GHZ states.
• The processor efficiently executes application benchmarks like QAOA and Hamiltonian simulations, paving the way for scalable, fault-tolerant quantum computing.

Analysis of the "Race Track Trapped-Ion Quantum Processor" Paper

The paper "A Race Track Trapped-Ion Quantum Processor" presents a comprehensive evaluation of a new quantum charge-coupled device (QCCD) trapped-ion quantum computer with a unique linear trap design featuring periodic boundary conditions resembling a race track. This research marks a notable advancement in scalable quantum computing architectures, highlighting several technological integrations and upgrades aimed at enhancing qubit scalability, gate fidelity, and operational efficiency.

Core Contributions and Key Features

1. Innovative Trap Design: The work centers on the introduction of a race track-shaped trap design that incorporates technology pivotal for scaling future QCCD systems. This includes:
   • Electrode broadcasting to minimize the number of independent voltage sources needed. This significantly reduces the control complexity as qubit numbers scale up.
   • Multi-layer RF routing allows RF voltage electrodes to be placed under the trapping surface, preventing obstructions at the top, which could otherwise impact the overall electric field shaping.
   • Magneto-Optical Trap (MOT) loading substitutes traditional ovens with a fast-loading mechanism, significantly improving ion loading times and hence, system efficiency. The MOT greatly increases neutral atom density, leading to faster ion loading.
2. Performance Metrics: The prototype system was evaluated with 32 qubits, demonstrating impressive metrics:
   • An average state preparation and measurement (SPAM) error of $1.6 \times 10^{-3}$.
   • An average single-qubit (1Q) gate infidelity of $2.5 \times 10^{-5}$.
   • An average two-qubit (2Q) gate infidelity of $1.84 \times 10^{-3}$.
3. System-Level Benchmarks: The quantum processor's capabilities were further validated via various system-level tests:
   • Quantum Volume (QV): Measured to be $2^{16}$, indicating the machine's high fidelity and connectivity.
   • Mirror Benchmarking and Cross-Entropy Benchmarking were employed to assess the processor's error rate under complex circuit operations, offering a real-world glimpse into its performance during computationally demanding tasks.
   • Generation of 32-qubit GHZ states, a significant milestone indicative of the entanglement capabilities over a larger qubit network.
4. Application Benchmarks: The processor demonstrated effectiveness in executing application-specific benchmarks such as Hamiltonian simulation, Quantum Approximate Optimization Algorithm (QAOA) tasks, quantum error correction via repetition codes, and dynamics simulations leveraging qubit reuse. The applications highlight the system's readiness for practical quantum computing tasks, bridging the gap between current feasible computations and the theoretical potential of quantum computing.

Implications and Future Prospects

The implications of this research are manifold:

• Scalability: The innovations in trap design pave a way to expand the qubit count and complex ion operations without proportional increases in control complexity or resource requirements.
• Operational Fidelity: High gate fidelity metrics positioned this system favorably for advanced error-corrected quantum algorithms, essential for practical and scalable quantum computing.
• Modular Advancements: The periodic upgradability of this system indicates that enhancements to qubit count and functionality can be implemented with minimal disruptions, suggesting a pathway from current device capabilities towards fully fault-tolerant quantum computations.

This research serves as a significant case paper and prototype for further developments in trapped-ion quantum processors, offering insights into the challenges and potential solutions for scaling quantum computers. Future work is directed towards integrating extensions for more qubits and exploring fully two-dimensional trap architectures for even more efficient qubit connectivity and operation.

Overall, the “Race Track Trapped-Ion Quantum Processor” encapsulates both a technical triumph in terms of enhancing QCCD architectures and an insightful guide for future innovations directed towards achieving fault-tolerant quantum computation.