Shuttling-based Distributed Quantum Computing

Updated 5 July 2026

SDQC is an architecture that employs physical qubit shuttling to mediate deterministic entanglement and nonlocal quantum logic between distinct processor modules.
Trapped-ion and semiconductor implementations demonstrate practical shuttling primitives with high fidelities, reducing wiring congestion and enabling scaled integration.
Advanced compilers and control protocols integrate shuttling with error correction and logical scheduling to optimize circuit depth and fault tolerance.

Searching arXiv for recent and foundational papers on shuttling-based distributed quantum computing and related architectures. Shuttling-based Distributed Quantum Computing (SDQC) uses physical transport of qubits as a quantum link between spatially separated processor “modules.” In the trapped-ion formulation, SDQC combines deterministic ion shuttling with a distributed, multi-core organization and gate teleportation, while in semiconductor implementations the same architectural idea appears as coherent spin shuttling, conveyor-mode channels, and shared-control shuttling links between qubit registers (Baek et al., 2 Dec 2025, Ademi et al., 30 Oct 2025).

1. Architectural concept and scope

SDQC replaces fixed nonlocal couplers with explicit motion. In the trapped-ion version, data qubits remain fixed in processor nodes, while entangled ion pairs are prepared in dedicated entanglement factories, shuttled through a network of segmented electrodes, and then consumed by gate-teleportation and syndrome-extraction circuits; detector chains are physically separated to avoid measurement-induced disturbance of the data register (Baek et al., 2 Dec 2025). In semiconductor realizations, the same role is played by moving electrons or holes in quantum dots, where the mobile carrier itself transports the qubit state between local register regions (Noiri et al., 2022).

This architectural stance is distinct from both monolithic nearest-neighbor arrays and photonic modularity. In QCCD-style ion processors, local full connectivity inside a trap is combined with inter-trap connectivity via split, move, and merge operations, so that shuttling is the communication layer between modules rather than an auxiliary calibration procedure (Zhu et al., 2 May 2025). In semiconductor devices, the analogous idea is a “quantum bus” or shared-control shuttling lane that links otherwise local spin-qubit registers while preserving the underlying qubit encoding (Seidler et al., 2021).

A recurrent systems-level motivation is that shuttling can relieve wiring pressure. One formulation emphasizes that qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms because it enables both crosstalk reduction and tighter integration of control hardware (Sun et al., 27 Jan 2026). Another emphasizes that small spin-qubit registers operate successfully, and that connecting these with a shuttling link is attractive provided the overhead of control signals stays moderate (Seidler et al., 2021). This suggests a characteristic SDQC design pattern: dense local registers, sparse transport corridors, and time-multiplexed motion as the source of effective connectivity.

2. Physical realizations and demonstrated primitives

The physical content of SDQC is best understood through the transport primitives that have already been demonstrated experimentally.

Platform	Demonstrated primitive	Representative result
Si/SiGe linear dot array	Charge shuttling through a 9-dot array	Single electron shuttled across 9 series-coupled Si quantum dots in $\sim 50$ ns (Mills et al., 2018)
Si/SiGe conveyor channel	Conveyor-mode single-electron transport	$420$ nm channel, four sinusoidal control signals, $99.42 \pm 0.02\%$ shuttling fidelity including reversal of direction (Seidler et al., 2021)
Si/SiGe triple dot	Shuttling-enabled two-qubit gate	Single-shuttle spin coherence preservation of $99.6\%$ and a controlled-phase gate fidelity of $93\%$ (Noiri et al., 2022)
Ge 2×2 dot array	Coherent spin-qubit shuttling	Spin-basis-state shuttling beyond $300~\mu\mathrm{m}$ effective length and coherent superposition shuttling to $49~\mu\mathrm{m}$ with dynamical decoupling (Riggelen-Doelman et al., 2023)
Ge distant registers	Shared-control inter-register shuttling link	Registers separated by more than one micrometer, transfer in approximately a hundred nanoseconds, Bell states across distinct registers (Ademi et al., 30 Oct 2025)

These demonstrations cover the main transport regimes used in SDQC. The 9-dot silicon experiment established the “bucket brigade” primitive: a sequence of pairwise interdot charge transfers down a calibrated array, together with a virtual-gate framework explicitly described as scalable to larger 1D arrays and possibly 2D arrays (Mills et al., 2018). Conveyor-mode transport instead uses a propagating electrostatic wave to define a moving dot, requiring only four sinusoidal control signals independent of channel length, which directly targets the signal-fanout problem in scalable semiconductor architectures (Seidler et al., 2021).

The germanium results are significant because they demonstrate coherent shuttling in a material system with strong spin–orbit coupling. A hole spin qubit was shuttled through multiple dots while preserving both basis-state information and phase coherence, despite dot-dependent $g$ -tensors and large axis variations (Riggelen-Doelman et al., 2023). The subsequent shared-control link between distant Ge registers integrated this transport primitive with local control and tomography, realizing a basic modular semiconductor processor in which the shuttling channel is not merely a transport test structure but an operational quantum link (Ademi et al., 30 Oct 2025).

3. Control protocols, error mechanisms, and coherence preservation

A central technical issue in SDQC is that transport is not a purely orbital process. In silicon spin qubits, shuttling errors are tied to device-specific quantities such as valley splitting, tunnel coupling, and detuning ramps. In the parity-architecture analysis for a shuttling-based spin-qubit processor, the detailed error model identifies the probability distribution function of the valley splitting as the main limitation for performance, and the hardware-specific analysis estimates the errors during one round of Parity QAOA under that model (Ginzel et al., 2024). In a complementary single-qubit control study, shuttling-based EDSR is shown to be ultimately bottlenecked by spin-valley physics, with low-valley-splitting points producing LZSM-like interference unless pulse design is optimized (Pazhedath et al., 2024).

For moving-spin architectures, the transport control itself can become part of the gate set. In conveyor-type Ge links, the moving potential is defined by

$V_i(t) = -A_i \sin\left(\phi_i^0 - 2\pi f_c t\right),$

with phase-shifted clavier gates generating a traveling minimum across the channel (Ademi et al., 30 Oct 2025). The relevant spin Hamiltonian is explicitly position dependent,

$H(t) = \frac{1}{2}\mu_B \mathbf{B}^{\mathsf T}\mathbf{g}(\mathbf{r}(t))\boldsymbol{\sigma} = \frac{\hbar}{2}\Omega(t)\,\mathbf{n}(t)\cdot\boldsymbol{\sigma},$

so transport through an inhomogeneous $420$0-tensor landscape produces deterministic SU(2) rotations in addition to dephasing (Ademi et al., 30 Oct 2025). This is not an incidental imperfection: in Ge, the local Larmor frequency varies strongly and non-monotonically along the lane, and compensation requires explicit calibration of a recovery unitary.

In silicon conveyor-bus error models for QEC, shuttling dephasing can instead benefit from motional narrowing. A representative effective model is

$420$1

with $420$2, so longer shuttling distances average over more disorder rather than simply accumulating static dephasing linearly (Escofet et al., 20 Oct 2025). This does not remove transport noise, but it changes its scaling and partly explains why large shuttling distances can remain compatible with logical error suppression when velocities are high enough.

A common misconception is that shuttling fidelity should be evaluated only at the charge level. The silicon 9-dot experiment indeed measures charge pumping current rather than spin transport, but it explicitly frames the result as a path toward spin QST as long as the total shuttling time remains below $420$3 (Mills et al., 2018). Subsequent Ge and Si experiments move beyond that limitation by directly measuring spin preservation, phase coherence, and even entanglement after transport (Riggelen-Doelman et al., 2023, Noiri et al., 2022).

4. Distributed entanglement and nonlocal logic

The defining SDQC capability is not transport by itself but nonlocal quantum logic mediated by transport. In silicon, a minimal version was realized as a shuttling-based two-qubit logic gate for linking distant processors: a moving qubit is shuttled into adjacency, exchange is switched on geometrically, and a controlled-phase gate is executed before the qubit is returned (Noiri et al., 2022). In that experiment, the exchange on/off ratio exceeded $420$4, the residual sparse-state exchange was $420$5, the chosen operating point gave $420$6, and interleaved randomized benchmarking measured a CZ fidelity of $420$7 (Noiri et al., 2022).

The Ge shared-control link pushed the architecture to genuinely distributed entanglement. Two three-dot registers were connected by a $420$8 shuttling lane; a Bell state was prepared locally, one qubit was transported into the remote register, and full two-qubit tomography was performed across the separated modules (Ademi et al., 30 Oct 2025). The reported bare Bell-state fidelities were $420$9, $99.42 \pm 0.02\%$ 0, $99.42 \pm 0.02\%$ 1, and $99.42 \pm 0.02\%$ 2 for the four Bell states, all above the $99.42 \pm 0.02\%$ 3 entanglement threshold, while SPAM-corrected values reached approximately $99.42 \pm 0.02\%$ 4, $99.42 \pm 0.02\%$ 5, $99.42 \pm 0.02\%$ 6, and $99.42 \pm 0.02\%$ 7 (Ademi et al., 30 Oct 2025).

In trapped ions, the same function is realized by moving entangled ancillas rather than data qubits. The SDQC proposal for trapped ions prepares Bell pairs in entanglement factories, shuttles the two ions of the pair to separate processor nodes, performs local interactions with stationary data qubits, and completes a nonlocal gate by measurement and feedforward (Baek et al., 2 Dec 2025). For a 256-bit ECDLP instance requiring $99.42 \pm 0.02\%$ 8 logical qubits at code distance $99.42 \pm 0.02\%$ 9, this architecture yields a logical error rate $99.6\%$ 0 of the photonic-DQC error rate and $99.6\%$ 1 of the QCCD error rate, while providing $99.6\%$ 2 times faster logical clock speed than QCCD (Baek et al., 2 Dec 2025).

This contrast illustrates two SDQC design choices. One can move the data qubit itself, as in spin buses and QCCD-like exchange links, or one can keep the data stationary and move entangled ancillas, as in trapped-ion SDQC. The former preserves encoding simplicity; the latter localizes the risk of transport error to expendable communication qubits. Both are genuine shuttling-based implementations of distributed logic.

5. Fault tolerance, logical architectures, and code-specific designs

Shuttling becomes architecturally consequential when it changes the asymptotics of fault-tolerant computation. In a segmented trapped-ion processor, a fault-tolerant weight-4 parity check with an additional flag qubit was demonstrated by dynamically reconfiguring the ion register through move, separate, merge, and physical-swap primitives around a single LIZ (Hilder et al., 2021). The flag-conditioned parity-measurement single-shot fidelity was $99.6\%$ 3, and the same circuit was benchmarked by witnesses that certified genuine six-qubit multipartite entanglement with $99.6\%$ 4 (Hilder et al., 2021). The significance for SDQC is that routing overhead did not preclude fault-tolerant stabilizer extraction.

At the logical-code level, several architectures use shuttling to change the geometry of QEC itself. A one-dimensional shuttling bus for the rotated surface code maps the 2D stabilizer schedule onto a monotone 1D motion pattern and, with optimized or Zig-Zag placement, reaches logical error rates as low as $99.6\%$ 5 per round at code distance $99.6\%$ 6 under the stated noise model (Escofet et al., 20 Oct 2025). A separate folded-surface-code architecture uses short-range shuttling in looped pipelines to realize effective three-dimensional connectivity on strictly two-dimensional hardware, reducing the runtime of all single-qubit logical Clifford gates and certain logical CNOTs from $99.6\%$ 7 in conventional lattice surgery to constant time (Sun et al., 27 Jan 2026). In that setting, access to a transversal $99.6\%$ 8 gate reduces the spacetime volume of 8T-to-CCZ distillation by more than an order of magnitude relative to standard 2D lattice-surgery approaches (Sun et al., 27 Jan 2026).

Shuttling also expands the code family beyond local surface codes. On a tileable spin-qubit chip with mobile ancillas, the CAbLECAR work tailors syndrome-extraction circuits to the shuttling noise model and extends the feasible shuttling range by $99.6\%$ 9– $93\%$ 0, enabling QLDPC codes with long-range checks (Chadwick et al., 27 Apr 2026). The resulting schedules are reported to be up to $93\%$ 1 faster than hand-optimized schedules for certain code families, and detailed circuit-level simulations identify QLDPC codes that improve upon prior surface-code implementations by orders of magnitude in logical error rate while increasing encoding efficiency (Chadwick et al., 27 Apr 2026).

Algorithm-specific architectures occupy an intermediate point. The parity architecture implemented on a shuttling-based spin processor realizes Parity QAOA on a lattice of identical unit cells with circuit depth always constant, includes a hardware-specific valley-splitting error model, and finds a parameter regime in which high-fidelity spin shuttling makes the performance competitive with or better than a superconducting transmon chip for the targeted workload (Ginzel et al., 2024). This is not a full fault-tolerant construction, but it demonstrates the same architectural thesis: transport can change algorithmic depth, not merely the placement of qubits.

6. Compilation, scheduling, and system-level trade-offs

Because transport is expensive, SDQC is fundamentally a compilation problem. A trapped-ion compiler targeting a shuttling-based processor with a single LIZ was built on top of Pytket and combined native-gate rebasing, SWAP elimination via qubit relabeling, phase tracking for virtual $93\%$ 2 gates, and “block aggregation” that clusters identical local rotations around two-qubit gates so that they can be executed while the relevant ions are already co-located (Kreppel et al., 2022). Across a wide range of circuits, this compiler reduced gate counts by factors up to $93\%$ 3 relative to standard Pytket and up to $93\%$ 4 relative to standard Qiskit compilation (Kreppel et al., 2022).

In QCCD, S-SYNC makes the same point at the movement layer by co-optimizing shuttling and SWAP operations on a static weighted graph that represents traps, spaces, and inter-trap channels (Zhu et al., 2 May 2025). The average shuttling count is reduced by $93\%$ 5, and the success rate improves by $93\%$ 6 on average (Zhu et al., 2 May 2025). The physical rationale is explicit: shuttling increases thermal motion, and gate fidelity is modeled as

$93\%$ 7

so reducing transport directly lowers subsequent gate error as well as runtime (Zhu et al., 2 May 2025).

For shuttling-based spin fabrics, the corresponding abstraction is multi-agent path planning. Q-SIPP in CAbLECAR treats mobile ancillas as agents moving through a tiled graph with safe intervals on channels and intersections, using A*-style search with a TSP-based admissible heuristic to produce time-ordered, collision-free syndrome schedules (Chadwick et al., 27 Apr 2026). The schedules for codes with up to $93\%$ 8 data qubits and $93\%$ 9 ancillas are found in under $300~\mu\mathrm{m}$ 0 minutes on a single core, and the mean shuttle count per ancilla is only about $300~\mu\mathrm{m}$ 1 above an ideal collision-free lower bound (Chadwick et al., 27 Apr 2026).

A recurring systems trade-off is that reducing shuttling can increase local congestion or gate time. In QCCD, larger modules reduce inter-trap transport but slow down entangling gates because gate time scales with chain length under some modulation schemes; in shuttling-bus surface-code mappings, poor placements can push the architecture below threshold even when the underlying physical error rates are otherwise acceptable (Zhu et al., 2 May 2025, Escofet et al., 20 Oct 2025). This suggests that SDQC performance is not a monotone function of “less movement.” The relevant design variable is the co-optimized tuple of module size, transport topology, routing freedom, and code schedule.

The principal open constraint is therefore not whether shuttling works as a primitive—it does across ions, silicon electrons, and germanium holes—but whether transport-aware compilation, noise tailoring, and hardware topology can keep movement-induced error below the point where its connectivity advantage is lost. Current results support a qualified positive answer: deterministic transport can already distribute entanglement between distant semiconductor registers, enable constant-depth logical primitives on 2D hardware, and improve fault-tolerant scheduling when the architecture is co-designed with the transport physics (Ademi et al., 30 Oct 2025, Sun et al., 27 Jan 2026, Chadwick et al., 27 Apr 2026).