Field-Programmable Gate Arrays (FPGAs)

Updated 5 December 2025

Field-Programmable Gate Arrays are reconfigurable semiconductors composed of CLBs, DSP slices, and BRAM, enabling custom hardware acceleration.
They support multiple programming models including RTL and HLS, which allow fine-grained parallelism and deterministic low-latency processing.
FPGAs excel in applications like scientific computing, deep learning, and signal processing by balancing reconfigurability, performance, and energy efficiency.

Field-Programmable Gate Arrays (FPGAs) are reconfigurable semiconductor devices defined post-manufacturing by configuration bitstreams that establish both digital logic and custom interconnects. Unlike CPUs or GPUs, which have fixed microarchitectures, FPGAs consist of dense arrays of programmable logic blocks, interspersed with hard arithmetic blocks (“DSPs”) and embedded SRAMs (“BRAM”). Configuration memory (typically SRAM) specifies the circuit, enabling development of bespoke, spatial dataflow hardware tailored to a specific workload. This architectural malleability situates FPGAs as an intermediary between general-purpose processors and ASICs, enabling domain-specific acceleration with rapid prototyping and deployment cycles. FPGAs support fine-grained parallelization, deterministic low-latency execution, direct interfacing with diverse external I/O, and—in large, contemporary devices—co-integration with hard CPU cores and domain-specialized compute fabrics.

1. FPGA Architectural Primitives and Configuration

A modern FPGA comprises four principal primitives:

Configurable Logic Blocks (CLBs) and Logic Elements (LEs): CLBs cluster LEs, each comprising a K-input lookup table (LUT) plus flip-flop(s). LUTs implement arbitrary K-input Boolean functions, programmed via configuration SRAM. Dedicated carry-chains accelerate adders and counters, while “fracturing” permits multiple, smaller LUTs to fit alternative patterns. CLBs interact with the routing matrix—hierarchies of mux-controlled switch boxes—which dominate overall area and parasitic load. Dynamic power is approximately $P_{\mathrm{dynamic}} = \alpha C V^2 f$ , with routing capacitance $C$ a significant factor (Boutros et al., 15 Apr 2024).
DSP Slices: DSPs are hardwired multipliers and adders (e.g., 25×18, 27×27, or pipelined MACs) with flexible pre- and post-adds, registers, and, in recent generations, selectable tiling modes to support low-precision arithmetic (e.g., int8, int4) and coarse-grained systolic interconnect (Boutros et al., 15 Apr 2024).
Block RAMs (BRAMs): On-chip SRAM blocks (e.g., 18 Kb, 36 Kb) support dual-port access, can be concatenated for depth or width, and often serve as weight/activation buffers, line buffers, or ROMs in accelerator designs.
Programmable Routing Fabric: All logic, memory, and I/O are interconnected via a grid of switchboxes multiplexed by configuration SRAM bits. Routing design (richness, long lines vs. local) governs maximum placeable logic, attainable fmax, and energy efficiency.

This reconfigurability enables hardware designers to instantiate full spatial dataflow graphs directly in fabric, eliminating fetch/decode/execute overhead. At the die level, area and power costs are increased relative to ASICs but amortized by multiple reuse “applications” (over the device’s operational lifetime) and deployment in mutable or rapidly evolving workloads (Boutros et al., 15 Apr 2024).

2. Design, Programming Models, and Compilation Flows

FPGA programming can proceed at multiple abstraction levels:

RTL (Verilog/VHDL): Allows cycle-accurate, bottom-up circuit design, optimal for high-performance or logic/placement-critical workloads (e.g., custom fixed-point or floating-point datapaths) (Lv et al., 9 Feb 2024, Cardamone et al., 2018).
High-Level Synthesis (HLS): C/C++/SystemC or domain-specific languages (DSLs, e.g., RIPL (Stewart et al., 2015), hls4ml (Jwa et al., 2022)) are compiled to register-transfer logic, with pragmas controlling loop unrolling, pipelining, and memory partitioning. HLS enables algorithm-architecture co-design for pipelined dataflow accelerators, Monte Carlo kernels, ML inference engines, and more (Jiménez, 4 Nov 2025, Lv et al., 9 Feb 2024, Jwa et al., 2022).
Domain-Specific Frameworks: For deep learning, frameworks such as Vitis AI (Xilinx), SDAccel, hls4ml, and software-programmable overlays (NPUs) automate the construction of accelerator hierarchies, partition models, and handle quantization-aware transformations. Compilation occurs in two phases: model-to-HLS kernel, then HLS kernel(s)-to-bitstream. Partial reconfiguration further enables deployment of new kernel configurations in minutes (Jiménez, 4 Nov 2025, Boutros et al., 15 Apr 2024).

Algorithmic Skeletons (DSLs): Frameworks such as RIPL use skeletons (e.g., map, convolve, fold) to build streaming image/data pipelines. Each skeleton yields an actor in a dataflow network; downstream pipelines operate on streaming data, eliminating bulk intermediate storage (Stewart et al., 2015).

3. Performance, Energy Efficiency, and Scalability

FPGAs enable deep pipelining, spatial parallelism, and deterministic latency, making them especially effective where data-parallel or kernel-pipelined computations dominate:

Floating-Point and Arbitrary Precision Pipelines: Modern FPGAs support hundreds of pipelined double-precision operators. Deep unrolling enables initiation intervals (II) of one cycle, bounded only by pipeline fill latency and resource availability. For instance, a Virtex-6 implementation realized 213 double-precision FLOPs per cell update at 390 MHz, giving 27.7 GFLOP/s per processing element with sub-millisecond latency (Nagy et al., 2014). Tensor network solvers and many-body Monte Carlo simulations achieve 10× CPU performance and deterministic, low-jitter execution (Lv et al., 9 Feb 2024).
Energy Efficiency (TOPS/W): FPGAs typically yield 3–10× lower energy per operation than CPUs/GPUs on spatially parallel tasks, driven both by architectural specialization and by dataflow pipelines that minimize register/memory accesses (Jiménez, 4 Nov 2025, Cardamone et al., 2018). For VMC kernels: 5–10× better performance-per-watt than multicore CPUs, with overall ∼30× speedup (Cardamone et al., 2018).
Scaling and Heterogeneous Integration: FPGAs can scale across multiple sockets (e.g., one VMC “walker” or CNN sample per slot), and—when combined in system-on-chip (SoC) arrangements—pair programmable logic with hardened ARM/RISC-V cores and high-bandwidth network interfaces for near-sensor or edge inference (Jiménez, 4 Nov 2025). In many-body physics, pipelining allows $O(1)$ time-per-sweep, independent of simulated system size up to the resource capacity of the device (Lv et al., 9 Feb 2024).
Comparison Table: Performance and Energy Efficiency

Metric	FPGA	GPU	CPU
Latency (CNN inference)	17–23 μs/sample (Jwa et al., 2022, Jiménez, 4 Nov 2025)	~100 μs	80 μs
Throughput (CNN)	60–500 img/s (Jiménez, 4 Nov 2025)	50–200 img/s	20–100 img/s
TOPS/W	0.5	0.16	0.02
Determinism	Sub-cycle (<50 μs)	High jitter	Moderate jitter

Values from (Jiménez, 4 Nov 2025, Jwa et al., 2022, Boutros et al., 15 Apr 2024): actual numbers depend on network/deployment. Throughput figures are for batch=1 edge inference.

4. Major Application Areas

Scientific Computing: Monte Carlo, tensor networks, and finite-volume PDE solvers. Deeply pipelined datapaths and on-chip buffering minimize memory bandwidth, yielding up to 90× speedup versus single-core CPU baselines for unstructured Euler equations (Nagy et al., 2014).
Deep Learning and Inference: FPGAs efficiently implement low-batch, deterministic-latency pipelines for convolution, attention, or recurrent networks. Typical designs quantize weights/activations (4–8b) to maximize DSP and logic utilization. Fixed-point quantized models via QAT and hls4ml on Xilinx UltraScale+ achieved 23.4 μs per 64×64 ROI at 95% accuracy, with ∼40% DSP utilization (Jwa et al., 2022). Dataflow and overlay-style NPUs on Stratix 10 NX reach up to 4.8–17× GPU batch-1 speedups (Boutros et al., 15 Apr 2024).
Image and Signal Processing: DSLs (RIPL) generate dataflow pipelines for convolution and filtering; on-chip streaming and line buffers obviate intermediate image storage, supporting high frame rates atop limited BRAM (Stewart et al., 2015).
Control Systems and Instrumentation: FPGAs implement high-speed digital controllers tightly coupled to analog interfaces (e.g., digital-locked laser controllers with 0.7 MHz linewidth, 10 ms settling time (Jørgensen et al., 2016)), leveraging on-chip sine/cosine LUTs, PID blocks, and real-time streaming.
General-Purpose Computer Architecture: Emerging architectures integrate miniature FPGA fabrics within CPU cores to serve as dynamic ISA extension slots. Sections of the instruction set are implemented (“fast-reconfigured”) in on-die FPGA fabric, offering software-transparent context-switching and cacheable bitstreams, achieving up to 0.82× full-hardened performance for multiprogrammed workloads with fine-grained extensibility (Papaphilippou et al., 2022).

5. Environmental Sustainability and Life-Cycle Assessment

Recent quantitative models assess FPGAs’ total carbon footprint (CFP) across design, manufacturing, reconfiguration, operation, and end-of-life (Sudarshan et al., 2023). The GreenFPGA framework formalizes total lifetime CFP as: $C_\mathrm{FPGA} = C_{\mathrm{emb}} + \sum_{i=1}^{N_{\mathrm{app}}} (T_i \times C_{\mathrm{deploy},i})$ with $N_{\mathrm{app}}$ (distinct applications served, i.e., reconfigurations), $T_i$ the duration of each, and $C_{\mathrm{deploy},i}$ operational and development CFP per context. FPGAs amortize design and manufacturing emissions by covering multiple workloads. They surpass ASICs in total CFP for crypto from the first reconfiguration, for DNN when $N_{\mathrm{app}}\gtrsim6$ or $T_i\lesssim1.6$ yrs, and for low-volume/multi-tenant edge deployments. Only large-volume, single-use, or area-dominated (e.g., heavy imaging) applications favor ASICs in lifetime CFP (Sudarshan et al., 2023).

6. Emerging Trends: Heterogeneity, Low-Temperature and System Integration

Hybrid SoCs and 3D Integration: FPGAs increasingly co-integrate hard processors, mesh NoCs, and AI engines on the same die (e.g., Xilinx Versal ACAP, Intel Agilex 5). AI engines execute int8 MACs at GHz frequencies (>100 TOPS int8). On-die networks support both fixed-point systolic and flexible packet flows (Boutros et al., 15 Apr 2024). Interposer/3D assembly (EMIB/CoWoS) allows tight coupling of FPGA fabric to ASIC chiplets or HBM, delivering >10× latency and energy efficiency gains for AI/RNN inference.
Cryogenic and Space Applications: Board/silicon-level and HDL/hardware-method adaptations now enable FPGA operation down to 4 K. Techniques include multi-cycle synchronous resets, CRC-checked configuration frames, ring-oscillator-based delay calibration, and comparator-based LDO power regulation. At 4 K, LUT delay and jitter marginally improve; transceiver BER and eye height are enhanced, offering robust digital computation in deep cryogenic regimes (Lewis et al., 17 Apr 2025). This unlocks cryo-compatible logic for space instrumentation and quantum computing interfaces.
DL-Specific Block Enhancements: AI tensor blocks (AITB), shadow-multiplier logic, popcount compressors, and compute-in-memory BRAMs are emerging as in-fabric primitives to maximize MAC density, reduce area, and collapse data movement (Boutros et al., 15 Apr 2024). For instance, Stratix 10 NX AITB natively supports three int8 dot-products/cycle per block for 4.8–11× inference speedup over V100 GPUs.

7. Trade-Offs, Limitations, and Outlook

Latency-Throughput-Energy Trade-offs: FPGAs are preferred when sub-millisecond deterministic latency or low-batch, real-time throughput is paramount. GPUs surpass FPGAs in aggregate throughput on large batches due to many-core SIMD, but incur higher startup latency, non-deterministic execution, and unfavorable energy/operation for batch=1 (Jiménez, 4 Nov 2025, Boutros et al., 15 Apr 2024).
Precision-Resource Scaling: Aggressive quantization (4b, 8b, ternary, binary) and model pruning maximize resource utility. HLS and bit-serial accumulator designs enable support for novel quantized formats (fp8, bfloat16, etc.) (Jiménez, 4 Nov 2025, Jwa et al., 2022).
Scalability Constraints: On-chip memory capacity and placement/routing congestion remain primary bottlenecks, especially as pipeline unrolling deepens. Optimally partitioned buffering, layout-aware high-level compilation, and interconnect-aware dataflow synthesis are active research areas (Nagy et al., 2014, Lv et al., 9 Feb 2024, Boutros et al., 15 Apr 2024).
Programming Productivity: High-level and domain-specific DSLs/HLS flows (e.g., RIPL, hls4ml) provide an order of magnitude productivity boost, but may not always match handopt RTL in clock frequency/timing closure for large, irregular graphs or highly resource-constrained designs (Stewart et al., 2015, Jwa et al., 2022).
Deployment Ecosystem: Toolchain maturity for partial reconfiguration, software overlays, and automated model partitioning are rapidly improving, enabling field updates of deployed accelerators and flexibility in data center and edge topologies (Jiménez, 4 Nov 2025, Boutros et al., 15 Apr 2024).

Overall, FPGAs occupy a strategic niche in modern compute infrastructure, balancing reconfigurability, deterministic and low-latency processing, eco-sustainability in rapidly evolving domains, and expanding applicability through architectural and ecosystem innovation. The research trajectory points to heterogeneous, physically adaptable computing fabrics, with FPGAs as core adaptable acceleration substrates for scientific, AI/ML, and embedded systems (Boutros et al., 15 Apr 2024, Jiménez, 4 Nov 2025, Sudarshan et al., 2023).