Double-Transmon Coupler (DTC)

• Double-Transmon Coupler (DTC) is a tunable superconducting architecture that employs dual coupler transmons and an additional Josephson junction to create two interference pathways for achieving an internally defined zero-coupling state.
• It supports fast entangling operations using both dc-flux and parametric control, enabling high-fidelity gates (e.g., CZ and iSWAP) with gate times as low as 18–24 ns.
• Variants like the capacitively shunted DTC and multiplexed control-line designs enhance robustness, reduce residual interactions, and improve scalability in multi-qubit quantum processors.

Searching arXiv for papers on the Double-Transmon Coupler to ground the article in the current literature. The double-transmon coupler (DTC) is a tunable coupler architecture for superconducting quantum circuits in which two coupler transmons are joined by an additional Josephson junction in a flux-biased loop, and are in turn capacitively connected to data qubits. In the literature, the DTC is presented as a multimode interference-based coupler that can realize an internally defined zero-coupling state, suppress residual $ZZ$ interactions for highly detuned fixed-frequency qubits, and support fast entangling operations through either dc-flux or parametric control. Since its introduction, the architecture has evolved from a theoretical proposal for straddling-free high-fidelity gates to experimental CZ and iSWAP implementations, multiqubit analyses, capacitively shunted variants, multiplexed control-line schemes, and extensions to fluxonium processors and transmon–waveguide interfaces (Goto, 2022, Campbell et al., 2022, Kubo et al., 2024).

1. Architectural definition and physical layout

In its original form, the DTC couples two fixed-frequency computational transmons to a central four-junction network. Qubits 1 and 2 are each capacitively coupled to one coupler transmon, while the two coupler transmons are connected through an additional Josephson junction in a superconducting loop threaded by external flux $\Phi_{\rm ex}$. The simplified architecture therefore contains two data qubits, two coupler transmons, and a central loop junction; parasitic capacitances are included in the full circuit description (Goto, 2022).

Subsequent formulations emphasize the same physical content in different mode bases. One common representation treats the two internal coupler degrees of freedom as hybridized symmetric and antisymmetric modes, often denoted the $p$-mode and $m$-mode. In that description, the $m$-mode is flux tunable while the $p$-mode is nearly fixed, and the effective qubit–qubit interaction is produced by interference between these two mediation pathways (Li et al., 2024). A related modular description writes the central coupler as two transmon islands joined by a third Josephson junction in a three-junction dc-SQUID, with a fixed capacitive splitting $g_C$ and a flux-tunable inductive splitting $g_L(\Phi_e)$ (Campbell et al., 2022).

Experimental realizations retain this basic topology while differing in implementation details. A 2024 CZ-gate realization used two fixed-frequency data qubits, two coupler transmons sharing a loop bridged by JJ5, a fast flux line carrying both DC and AWG pulses, individual $\lambda/4$ readout resonators for the qubits, and a third resonator for the coupler modes, all coupled via a common Purcell filter (Li et al., 2024). A 2026 iSWAP experiment used two tunable data transmons and a four-junction DTC with two coupler transmons connected by a central Josephson junction, plus a dedicated DC flux line and RF port for high-speed modulation (Tiwari et al., 29 Apr 2026).

These descriptions establish that the DTC is not merely a replacement for a single tunable element. Its defining feature is the presence of two internal coupler modes or, equivalently, two interference pathways whose relative balance is adjusted by flux. A plausible implication is that the DTC should be understood as a multimode coupler family rather than as a single circuit instance.

2. Hamiltonian structure and coupling-cancellation mechanism

The circuit-theoretic starting point is a charge–phase Hamiltonian derived from the full node-flux or node-phase Lagrangian. In one common form,

$$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$

where the reduced external flux is $\Phi_{\rm ex}$0 (Li et al., 2024). Related derivations start from the full seven-node Lagrangian in multiqubit layouts and produce an analogous Hamiltonian containing the charging matrix, Josephson cosine terms, flux-drive terms, and microwave-drive terms (Kubo et al., 2024).

After mode reduction, one obtains a dressed description involving data-qubit modes and the two hybridized DTC modes. In the $\Phi_{\rm ex}$1 basis, the effective qubit–qubit exchange can be written as

$\Phi_{\rm ex}$2

with $\Phi_{\rm ex}$3. By tuning $\Phi_{\rm ex}$4 across $\Phi_{\rm ex}$5, the two contributions can cancel, producing an idle point with $\Phi_{\rm ex}$6 and strongly reduced residual $\Phi_{\rm ex}$7 even for qubits outside the straddling regime (Li et al., 2024). In the modular formulation, the same cancellation appears as the condition

$\Phi_{\rm ex}$8

so that the zero-coupling flux bias depends only on the coupler parameters and not on the coupled data-qubit frequencies (Campbell et al., 2022).

In dispersive analyses focused on residual longitudinal coupling, the effective two-qubit interaction is written as

$\Phi_{\rm ex}$9

with $p$0 at the “zero–ZZ” bias and only a small higher-order residual $p$1 remaining (Kubo et al., 2024). Numerical diagonalization in the original two-qubit DTC model found that $p$2 dips to about $p$3 kHz at $p$4 for $p$5 (Kubo et al., 2022).

The central theoretical point is therefore interference: the DTC suppresses residual coupling not by relying on a single cancellation between direct qubit–qubit capacitance and a tunable intermediate element, but by balancing multiple mediated paths internal to the coupler. This is the basis for the “internally defined” zero point emphasized in modular treatments (Campbell et al., 2022).

3. Gate modalities and reported performance

The DTC literature includes both flux-pulsed and parametrically driven entangling gates. In early two-qubit numerics, an ac flux pulse at the qubit detuning implemented a $p$6 gate with an average fidelity over $p$7 and a gate time of about $p$8 ns, while a dc flux pulse implemented a CZ gate with an average fidelity over $p$9 and a gate time of about $m$0 ns (Kubo et al., 2022). These proposals used highly detuned fixed-frequency qubits and treated the negligible idle residual $m$1 as a precondition for fast activation.

Experimental work established that the architecture can be realized in fabricated devices. A 2024 realization of a DTC-based CZ gate used a 48 ns “Slepian-like” pulse on the coupler loop together with virtual-$m$2 corrections, reporting $m$3 for the CZ and individual single-qubit RB fidelities of $m$4 and $m$5 (Li et al., 2024). In a separate three-qubit numerical study, two DTCs connecting three fixed-frequency qubits enabled 30-ns CZ gates and individual and simultaneous 10-ns $m$6 pulses with fidelities over $m$7 including spectator and leakage errors (Kubo et al., 2024).

Later variants broadened the operating regime. The capacitively shunted DTC (CSDTC) realized bias-free idling at zero flux and reported a 64 ns CZ gate with $m$8 (Li et al., 4 Mar 2025). A parametrically driven iSWAP gate operated at the zero-flux sweet spot of a CSDTC used second-harmonic modulation and achieved $m$9 at a total gate time of 112 ns, with leakage $m$0 and depolarization $m$1 (Inoue et al., 30 Apr 2026). Another 2026 experiment demonstrated a parametric iSWAP gate between two transmon qubits using a DTC, calibrated by robust phase estimation, and achieved a $m$2 gate fidelity in 40 ns without any numerical optimization (Tiwari et al., 29 Apr 2026).

Work	Gate or control mode	Reported result
(Kubo et al., 2022)	$m$3 via ac flux	about 24 ns, average fidelity over 99.99%
(Kubo et al., 2022)	CZ via dc flux	about 18 ns, average fidelity over 99.99%
(Li et al., 2024)	Experimental CZ	48 ns, 99.90%
(Kubo et al., 2024)	Three-qubit CZ and $m$4 pulses	30 ns CZ and 10 ns $m$5, fidelities over 99.99%
(Li et al., 4 Mar 2025)	CSDTC CZ	64 ns, 99.89%
(Tiwari et al., 29 Apr 2026)	Parametric iSWAP	40 ns, 99.827%
(Inoue et al., 30 Apr 2026)	Zero-flux CSDTC iSWAP	112 ns, 99.92(2)%

Across these reports, the DTC is used in three distinct control paradigms: direct conditional-phase accumulation by dc flux pulses, resonant exchange activated by parametric modulation, and zero-flux parametric exchange in the capacitively shunted variant. This suggests that the DTC is less a single gate prescription than a coupler platform supporting multiple gate families.

4. Multiqubit behavior and comparison with the single-transmon coupler

A central question for any tunable coupler is whether isolated two-qubit performance survives in a multiqubit environment. The 2024 three-qubit analysis addressed this explicitly for a chain of three fixed-frequency qubits coupled by two DTCs, with nearest-neighbor qubits highly detuned and next-nearest neighbors nearly resonant. The chosen bare frequencies were $m$6 GHz, $m$7 GHz, and $m$8 GHz; coupler transmons were set to $m$9 GHz with loop-junction ratio $p$0; nearest-neighbor coupling was approximately $p$1 MHz, and parasitic next-nearest coupling was approximately $p$2 MHz (Kubo et al., 2024).

For this system, the flux-tunable exchange satisfied $p$3 MHz to $p$4 MHz as $p$5 varied from $p$6 to $p$7, crossing zero at $p$8. At the idle point, the residual coupling was reported as $p$9 kHz for nearest neighbors and $g_C$0 kHz for the next-nearest pair. The same study reported 30-ns CZ gates on both nearest-neighbor pairs and 10-ns $g_C$1 rotations, both individual and simultaneous on any subset of $g_C$2, with fidelities over $g_C$3 (Kubo et al., 2024).

The comparison with the single-transmon coupler (STC) was particularly explicit. In the same three-qubit layout, the STC idle point produced $g_C$4 kHz and $g_C$5 kHz, versus $g_C$6 kHz for the DTC; for the next-nearest and three-body terms, $g_C$7 kHz and $g_C$8 kHz, both $g_C$9 kHz for the DTC. CZ(30 ns) fidelities dropped to $g_L(\Phi_e)$0 for the STC versus $g_L(\Phi_e)$1 for the DTC, and single-qubit $g_L(\Phi_e)$2 pulses degraded to $g_L(\Phi_e)$3 on $g_L(\Phi_e)$4 (Kubo et al., 2024).

The reported cause was geometric and electrostatic rather than merely algorithmic. In the STC, optimal cancellation required large direct capacitances $g_L(\Phi_e)$5 and $g_L(\Phi_e)$6, which forced $g_L(\Phi_e)$7 and $g_L(\Phi_e)$8 closer and produced a parasitic $g_L(\Phi_e)$9 MHz, ten times the DTC value. In the DTC, the architecture did not rely on direct $\lambda/4$0; the qubits could be spaced farther, with $\lambda/4$1 fF and $\lambda/4$2 MHz, and all residual $\lambda/4$3 terms could be tuned to essentially zero (Kubo et al., 2024).

A later multiplexed three-qubit experiment preserved the same DTC logic while sharing a single global $\lambda/4$4-control line between two couplers. In that system, the shared-line DTC achieved $\lambda/4$5 below 100 kHz for both $\lambda/4$6–$\lambda/4$7 and $\lambda/4$8–$\lambda/4$9 over the same $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$0-bias, and demonstrated CZ fidelities of $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$1–$$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$2, Bell-state fidelities of $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$3 and $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$4, and a three-qubit GHZ fidelity of $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$5 (Cai et al., 4 Nov 2025).

These results directly address a common misconception in tunable-coupler design: that cancellation verified in an isolated two-qubit subsystem automatically guarantees system-level suppression. The DTC studies show that parasitic geometry, next-nearest-neighbor spacing, and shared-control calibration remain decisive at the multiqubit level.

5. Variants and architectural generalizations

The most prominent variant is the capacitively shunted DTC. By adding a large shunt capacitance $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$6 in parallel with the central coupler junction, the CSDTC realizes bias-free idling at zero flux. In the zero-flux analysis,

$$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$7

and the residual interaction was reported as $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$8 MHz, i.e. about $$\hat H=\frac{(2e)^2}{2}\,\hat{\mathbf n}^T\,\mathsf C^{-1}\,\hat{\mathbf n} -\sum_{i=1}^4 E_{J,i}\cos\hat\varphi_i -E_{J,5}\cos(\hat\varphi_4-\hat\varphi_3-\varphi_{\rm ex}),$$9 kHz, at zero-flux bias (Li et al., 4 Mar 2025). The same work reported that this zero-coupling condition persists over a broad range $\Phi_{\rm ex}$00, with $\Phi_{\rm ex}$01 for any static offset $\Phi_{\rm ex}$02 and simultaneous single-qubit RB fidelity $\Phi_{\rm ex}$03 (Li et al., 4 Mar 2025).

The zero-flux operating point also enabled a distinct parametric iSWAP mechanism. In the 2026 CSDTC experiment, the $\Phi_{\rm ex}$04-mode frequency was an even function of flux, so a drive $\Phi_{\rm ex}$05 modulated $\Phi_{\rm ex}$06 at even harmonics. Choosing $\Phi_{\rm ex}$07 activated a second-harmonic iSWAP with total rate

$\Phi_{\rm ex}$08

while keeping the coupler participation $\Phi_{\rm ex}$09, compared with approximately $\Phi_{\rm ex}$10 for a baseband CZ waveform (Inoue et al., 30 Apr 2026). This suggests a trade-off between gate family and coupler hybridization that is specific to the DTC architecture.

Another generalization concerns control-line economy. The multiplexed DTC architecture routes a single DC+RF line from room temperature, then splits it on-chip into multiple branches, each threading one DTC SQUID, with fully-capped air-bridges enforcing equal potential ground and suppressing microwave crosstalk. In a 1D chain of $\Phi_{\rm ex}$11 qubits, this reduces the number of coupler $\Phi_{\rm ex}$12 lines from $\Phi_{\rm ex}$13 in an STC scheme to $\Phi_{\rm ex}$14; in a 2D square lattice, row-wise sharing reduces the count from approximately $\Phi_{\rm ex}$15 to $\Phi_{\rm ex}$16 (Cai et al., 4 Nov 2025).

The DTC has also been repurposed beyond transmon–transmon gates. In a transmon emitter/detector architecture, the DTC acted as a compact, drop-in, tunable and transition-selective link between a coherent transmon and a continuum of waveguide modes. Two nominally identical DTC-based transmon emitter/detectors connected by a meter of coaxial cable and a circulator detected $\Phi_{\rm ex}$17 of the photons, with an inferred $\Phi_{\rm ex}$18 detection probability at the input of the measurement device; reset and photon emission/detection each required about $\Phi_{\rm ex}$19s, for a minimum protocol duration of $\Phi_{\rm ex}$20s (Campbell et al., 16 Jan 2026).

These variants show that the DTC concept has broadened in two directions: toward bias-robust and wiring-efficient superconducting processors, and toward tunable interfaces between protected qubits and other circuit degrees of freedom.

6. Scalability, limitations, and broader significance

The DTC is regularly positioned as a scalability-oriented alternative to the STC because it combines strong tunability with broad residual-coupling suppression for highly detuned qubits. In modular form, its zero-coupling point is independent of the data-qubit frequencies, which is why the architecture is described as “qubit-agnostic” and “internally defined” (Campbell et al., 2022). In the three-qubit fixed-frequency analysis, this translated into out-of-straddling operation with nearest-neighbor detunings of 500 MHz and 490 MHz, yet still with 30-ns CZ gates and negligible idle residuals (Kubo et al., 2024).

A system-level extension to fluxonium processors pushes the same logic into a different qubit modality. There, DTCs are used in a frequency-partitioned architecture that separates qubit transitions, tunable-coupler excitations, and resonator modes into disjoint spectral regions. The resulting multi-objective design yielded $\Phi_{\rm ex}$21, $\Phi_{\rm ex}$22 for a MAP gate, $\Phi_{\rm ex}$23, $\Phi_{\rm ex}$24 kHz, $\Phi_{\rm ex}$25 ns with $\Phi_{\rm ex}$26, and $\Phi_{\rm ex}$27 MHz with $\Phi_{\rm ex}$28 (Chan et al., 29 Apr 2026). This suggests that the DTC is being treated not only as a gate primitive but as a processor-level architectural component.

The principal limitations reported in the literature are likewise consistent across variants. Coupler coherence is identified as a dominant fidelity limiter in the all-microwave fixed-frequency coupler experiment, where $\Phi_{\rm ex}$29 had $\Phi_{\rm ex}$30s and was stated to limit ultimate CZ fidelity (Shirai et al., 2023). In the 2024 experimental CZ based on the DTC, the measured gate-length dependence implied an effective $\Phi_{\rm ex}$31s during pulsing, whereas the measured idle $\Phi_{\rm ex}$32 of the qubits predicted $\Phi_{\rm ex}$33s, pointing to additional decoherence when the coupler is pulsed (Li et al., 2024). The CSDTC work similarly concluded from a randomized-benchmarking error budget that current fidelity was limited by decoherence through the coupler (Li et al., 4 Mar 2025).

Other recurring constraints are calibration and matching. The multiplexed architecture requires careful pre-fabrication matching of $\Phi_{\rm ex}$34 so that cancellation points align, post-fabrication calibration of a global flux offset, and compensation of spectator phase shifts (Cai et al., 4 Nov 2025). Parametric iSWAP operation with a DTC required robust phase estimation because $\Phi_{\rm ex}$35 and exchange $\Phi_{\rm ex}$36 errors do not commute, so conventional repetition rotates both eigenvalues and eigenvectors (Tiwari et al., 29 Apr 2026). Zero-flux CSDTC iSWAP operation was motivated partly by the observation that large-amplitude baseband flux pulses are vulnerable to pulse distortion and decoherence due to large qubit–coupler hybridization (Inoue et al., 30 Apr 2026).

Taken together, these studies define the DTC as a multimode tunable-coupler architecture whose main technical claim is not simply fast entangling gates, but fast entangling gates together with a robust off state for highly detuned qubits and reduced sensitivity to layout-induced parasitics. The remaining challenge is therefore not proof of principle, but the simultaneous optimization of coupler coherence, control simplicity, wiring overhead, and fabrication robustness in larger processor-scale deployments.