LUT-Assisted Delay Shaping

• LUT-assisted delay shaping is a family of techniques that use compact table-based representations to explicitly control delay-dependent behavior across diverse domains.
• In power amplifier DPD, spline-interpolated LUTs combined with FIR filters or delay branches efficiently shape nonlinear memory responses while reducing computational cost.
• In FPGA mapping, on‐the-fly Ashenhurst–Curtis decomposition restructures Boolean functions via two-level LUT networks to minimize logical path delays and improve critical timing.

LUT-assisted delay shaping denotes a family of techniques in which lookup tables (LUTs) are used to control delay-dependent behavior, but the term is not tied to a single research lineage. In the cited literature, it appears in at least three technically distinct settings: power-amplifier digital predistortion (DPD), where spline-interpolated complex LUTs are combined with FIR filters or delay lines to shape nonlinear memory response; delay–Doppler waveform generation, where precomputed delay-domain pulse-shaping kernels are stored in LUT form and applied under circular or linear filtering models; and FPGA technology mapping, where LUT realizations are structurally decomposed to reshape logic-path delay on critical paths (Campo et al., 2019, Bayat et al., 2023, Calvino et al., 2024). The common thread is not a shared signal model, but the use of LUT-mediated representations to make delay behavior explicit, controllable, and computationally efficient.

1. Terminological scope and cross-domain meaning

The cited literature suggests that “LUT-assisted delay shaping” is best understood as an umbrella description rather than a canonical method. In wideband RF linearization, LUT assistance refers to a complex envelope-indexed nonlinearity whose output is followed by either a common FIR filter or a bank of delayed branches, so that the effective predistorter memory response is shaped by post-LUT dynamics (Campo et al., 2019). In delay–Doppler modulation, LUT assistance refers to storing pulse-shaping kernels indexed by delay, and in the ODDM case by both delay and Doppler, so that pulse-shaping along the delay dimension can be implemented without on-the-fly filter generation (Bayat et al., 2023). In delay-driven LUT mapping for logic synthesis, the term refers to decomposing Boolean functions into two-level LUT structures so that critical inputs traverse fewer LUT levels than non-critical inputs, thereby reshaping the propagation-delay profile (Calvino et al., 2024).

A concise comparison is given below.

Domain	LUT role	Delay-shaping objective
PA DPD	Complex spline-interpolated nonlinear mapping	Shape nonlinear memory response
Delay–Doppler pulse-shaping	Stored delay-domain shaping kernels	Control boundary behavior, OOB, and filtering along delay
FPGA LUT mapping	Structural realization of decomposed Boolean functions	Reduce critical-path logical depth

This comparison suggests a useful unifying interpretation: LUTs serve as compact parameterizations of functions whose interaction with delay, memory, or path depth is the primary optimization target. A plausible implication is that the phrase should always be interpreted relative to its application domain, because the underlying state variables, constraints, and performance metrics differ substantially.

2. Power-amplifier predistortion: spline-LUT memory shaping

In the DPD setting, LUT-assisted delay shaping is explicitly a method for counteracting nonlinear distortion with memory in wideband power amplifiers. The purpose is to generate a counter-distortion with a tailored memory response for effects such as frequency-dependent AM-AM and AM-PM, envelope-dependent group delay, and bias or thermal effects. The basic mechanism combines a complex spline-interpolated LUT implementing a static input–output nonlinearity indexed by signal envelope with a delay-shaping element that supplies the memory response (Campo et al., 2019).

Two architectures are defined. The spline-based Hammerstein (SPH) approach uses the signal flow

$$x[n] \rightarrow \text{complex spline-interpolated LUT} \rightarrow h[k] \rightarrow y[n],$$

where the LUT is injection-based:

$u[n] = x[n] + x[n] g_n^T c,$

and the FIR filter shapes memory as

$y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$

The spline-based memory polynomial (SMP) approach replaces the common FIR with $M$ delayed branches, each with its own complex spline-LUT:

$u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$

$$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$

In SPH, memory shaping is global because the FIR $h[k]$ controls the effective response after a single LUT. In SMP, memory shaping is delay-selective because each delay $m$ has its own branch-specific complex control vector $q_m$ (Campo et al., 2019).

The spline interpolation itself is defined over uniform envelope regions spanning $0 \le |z[n]| \le A_{\max}$, with region index and local abscissa

$u[n] = x[n] + x[n] g_n^T c,$0

The basis vector is

$u[n] = x[n] + x[n] g_n^T c,$1

with $u[n] = x[n] + x[n] g_n^T c,$2, and the complex LUT output is injection-based:

$u[n] = x[n] + x[n] g_n^T c,$3

Because $u[n] = x[n] + x[n] g_n^T c,$4 is the deviation from unity, initializing $u[n] = x[n] + x[n] g_n^T c,$5 yields $u[n] = x[n] + x[n] g_n^T c,$6, which gives a unit baseline. The paper emphasizes that this reduces the dynamic range of LUT entries and decouples gain from memory shaping, leaving the FIR or delayed branches solely responsible for the memory response (Campo et al., 2019).

The relation to ordinary memory polynomial (MP) DPD is central. Ordinary MP is

$u[n] = x[n] + x[n] g_n^T c,$7

SMP replaces the monomials $u[n] = x[n] + x[n] g_n^T c,$8 with spline-interpolated LUTs $u[n] = x[n] + x[n] g_n^T c,$9. According to the paper, this maintains amplitude and phase flexibility with fewer operations and no basis-orthogonalization, while keeping linearization capability very close to ordinary MP, particularly for SMP (Campo et al., 2019).

3. Gradient-adaptive estimation and implementation in DPD

The DPD paper derives per-sample complex gradient updates in an indirect learning architecture (ILA). With error

$y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$0

the SPH updates are

$y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$1

$y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$2

where $y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$3 stacks the spline basis vectors over memory and $y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$4 is a diagonal matrix of delayed input samples. The SMP branch-wise update is

$y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$5

These are explicitly characterized as LMS-like complex gradient updates, and the paper states that no orthogonalization is needed (Campo et al., 2019).

The implementation details are closely tied to the injection-based formulation. Complex control points $y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$6 and $y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$7 encode both AM-AM and AM-PM. Uniform splines are used, and only $y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$8 control points contribute per region, so the main-path per-sample compute cost does not depend on total $y[n] = \sum_{k=0}^{K-1} h[k]u[n-k].$9. The basis has the partition-of-unity property $M$0 for classic B-splines, while the deviation form $M$1 removes DC or overall gain impact from the LUT. Practical guidance in the paper includes initializing $M$2 and $M$3 to zero, initializing $M$4 to a causal lowpass or shaping filter, gradually increasing step sizes, monitoring error power, and clipping updates if needed (Campo et al., 2019).

The reported complexity reductions are explicit. For the numerical example $M$5, $M$6, $M$7, SPH requires 40 real multiplications per sample in the main path and 124 in learning. For $M$8, $M$9, $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$0, SMP requires 63 real multiplications per sample in the main path and 119 in learning. The MP reference with $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$1, $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$2 requires 112 real multiplications per sample in the main path and 2514 in learning. The corresponding reported reductions versus MP are $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$3 for SPH and $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$4 for SMP in the main path, and $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$5 for SPH and $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$6 for SMP in learning. The paper also gives FLOPs per sample for one experimental setting: 69 for SPH with $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$7; 99 for SMP with $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$8; and 255 for MP (Campo et al., 2019).

Experimentally, the methods are evaluated on multiple sub-6 GHz PA samples and a 28 GHz active antenna array with bandwidths up to 200 MHz. For a Mini-Circuits ZHL-4240 at 3.5 GHz, 100 MHz channel bandwidth, and $u_m[n] = x[n-m] + x[n-m] g_{n-m}^T q_m,$9 dBm, the reported EVM values are 5.54 for SPH, 5.57 for SMP, and 5.47 for MP; the maximum adjacent-channel spectral density ranges are $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$0 to $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$1 dBm/MHz for SPH, $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$2 to $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$3 dBm/MHz for SMP, and $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$4 dBm/MHz for MP. For a Skyworks PA at 3.65 GHz, 100 MHz, and $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$5 dBm, EVM is 5.57 for SPH, 5.55 for SMP, and 5.54 for MP. In OTA measurements with an Anokiwave AWMF-0129 28 GHz active antenna array at EIRP $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$6 dBm, no DPD gives about 26 dB ACLR and about 12% EVM; for 100 MHz, SPH gives 34.4 dB ACLR and 6.20% EVM, SMP gives 34.8 dB and 6.15%, and MP gives 35.2 dB and 6.00%; for 200 MHz, SPH gives 34.1 dB and 6.25%, SMP gives 34.4 dB and 6.20%, and MP gives 35.0 dB and 6.13% (Campo et al., 2019).

These results support a domain-specific meaning of LUT-assisted delay shaping: the LUT does not merely approximate a static nonlinearity; it is part of a composite structure in which memory response is deliberately assigned either to a post-LUT FIR or to delay-indexed LUT branches.

4. Delay–Doppler pulse-shaping with LUT-stored kernels

In delay–Doppler waveform design, LUT-assisted delay shaping refers to storing pulse-shaping kernels for filtering along the delay dimension. The underlying framework places symbols on a regular delay–Doppler grid $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$7, maps them by an $$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$8-point IDFT along the Doppler dimension,

$$y[n] = \sum_{m=0}^{M-1} u_m[n] = x[n] + \sum_{m=0}^{M-1} x[n-m] g_{n-m}^T q_m.$$9

and serializes $h[k]$0 with $h[k]$1. An oversampling factor $h[k]$2 expands the delay dimension to $h[k]$3, and pulse-shaping is applied along the expanded delay coordinate using a Nyquist filter $h[k]$4, such as RRC, optionally truncated to $h[k]$5 zero-crossings (Bayat et al., 2023).

The generalized framework distinguishes circular pulse-shaping (C-PS) and linear pulse-shaping (L-PS). In C-PS, filtering is an $h[k]$6-point circular convolution:

$h[k]$7

with transmit block

$h[k]$8

In L-PS, filtering is non-cyclic:

$h[k]$9

followed by overlap-and-add:

$m$0

The paper states that circular pulse-shaping has cyclic wrap-around within each $m$1-sample delay block, causing abrupt edges and high out-of-band (OOB) emission unless guards are added, whereas linear pulse-shaping preserves smooth pulse transients and thus yields lower OOB, at the cost of truncation-induced approximation error when $m$2 is small or constellations are large (Bayat et al., 2023).

Within this framework, ODDM is derived as a linear pulse-shaping technique. The delay-domain shaping filters become Doppler dependent:

$m$3

and the discrete-time ODDM transmit signal is written as

$m$4

The paper attributes the staircase behavior of the ODDM spectrum to these Doppler-dependent shaping filters, because the average power spectrum aggregates shifted copies of $m$5 (Bayat et al., 2023).

The LUT-assisted implementation is concrete. For C-PS OTFS, one precomputes a cyclic pulse LUT over $m$6, optionally including cyclic shifts or FFT-domain representations. For L-PS OTFS, one stores a truncated pulse LUT over $m$7, where $m$8. For ODDM, one stores Doppler-modulated pulses $m$9 for $q_m$0 and $q_m$1. The transmitter then performs delay upsampling, accesses the relevant LUT entries by delay and, in ODDM, by Doppler, applies the corresponding circular or linear convolution, uses overlap-and-add across time-slots, and finally inserts the CP (Bayat et al., 2023).

Zero-guard (ZG) insertion is part of the same delay-shaping framework. Setting

$q_m$2

suppresses cyclic wrap-around of pulse transients into the data-bearing region and effectively introduces smooth ramps at delay-block boundaries. For $q_m$3, $q_m$4, $q_m$5, RRC roll-off 0.1, truncation $q_m$6, EVA channel, $q_m$7 GHz, $q_m$8 kHz, $q_m$9 km/h, CP longer than channel spread, and MMSE equalization, inserting $0 \le |z[n]| \le A_{\max}$0 zero-guards at both edges reduces OOB by up to approximately 20 dB for C-PS OTFS and improves BER by approximately 2 dB for 16-QAM and approximately 1 dB for 4-QAM at the same $0 \le |z[n]| \le A_{\max}$1 across C-PS, L-PS, and ODDM. The efficiency becomes

$0 \le |z[n]| \le A_{\max}$2

which is about 0.94 for $0 \le |z[n]| \le A_{\max}$3 and $0 \le |z[n]| \le A_{\max}$4 (Bayat et al., 2023).

Here, “delay shaping” has a different meaning than in DPD. It concerns the shaping of delay-domain pulse transients, boundary conditions, and spectral containment rather than nonlinear memory inversion. The commonality lies in the use of precomputed LUT content to make delay-domain operations efficient and structured.

5. Delay-driven logic synthesis: Ashenhurst–Curtis decomposition for path-delay shaping

In FPGA technology mapping, LUT-assisted delay shaping refers to restructuring combinational logic so that the maximum arrival time at outputs is reduced under $0 \le |z[n]| \le A_{\max}$5-input LUT constraints. The mechanism described in the cited work is Ashenhurst–Curtis decomposition (ACD), performed on the fly during mapping. The central idea is to decompose a Boolean function into a two-level LUT network in which late-arriving inputs traverse one LUT level while other inputs may traverse two levels, thereby reducing critical-path depth without indiscriminate duplication (Calvino et al., 2024).

The formal decomposition begins with a partition $0 \le |z[n]| \le A_{\max}$6, giving the classical form

$0 \le |z[n]| \le A_{\max}$7

The generalized form used in the paper introduces bound, shared, and free sets:

$0 \le |z[n]| \le A_{\max}$8

where $0 \le |z[n]| \le A_{\max}$9 may be a vector of $u[n] = x[n] + x[n] g_n^T c,$00 single-output BS functions and $u[n] = x[n] + x[n] g_n^T c,$01 is the composition function. For a partition $u[n] = x[n] + x[n] g_n^T c,$02, the Ashenhurst matrix has $u[n] = x[n] + x[n] g_n^T c,$03 rows and $u[n] = x[n] + x[n] g_n^T c,$04 columns, and if the number of distinct columns is $u[n] = x[n] + x[n] g_n^T c,$05, then the minimum number of BS functions satisfies

$u[n] = x[n] + x[n] g_n^T c,$06

The paper gives LUT-feasibility conditions such as

$u[n] = x[n] + x[n] g_n^T c,$07

and, in its truth-table formulation, acceptance criteria stated as $u[n] = x[n] + x[n] g_n^T c,$08 and $u[n] = x[n] + x[n] g_n^T c,$09 (Calvino et al., 2024).

The delay model is a simplified unit-delay model for $u[n] = x[n] + x[n] g_n^T c,$10-LUT mapping with $u[n] = x[n] + x[n] g_n^T c,$11 and interconnect ignored. For a mapped network,

$u[n] = x[n] + x[n] g_n^T c,$12

but the evaluation itself uses the unit-delay abstraction. During on-the-fly ACD on a cut of size $u[n] = x[n] + x[n] g_n^T c,$13, the mapper identifies late leaves $u[n] = x[n] + x[n] g_n^T c,$14, forces them into the free set $u[n] = x[n] + x[n] g_n^T c,$15, and seeks a two-level implementation in which free-set inputs incur a delay increase of one level while other signals incur a delay increase of two levels. The propagation profile is therefore:

• inputs in $u[n] = x[n] + x[n] g_n^T c,$16: $u[n] = x[n] + x[n] g_n^T c,$17;
• inputs in $u[n] = x[n] + x[n] g_n^T c,$18 and non-buffered shared inputs: $u[n] = x[n] + x[n] g_n^T c,$19 (Calvino et al., 2024).

The on-the-fly evaluation avoids full encoding during mapping. For each large cut $u[n] = x[n] + x[n] g_n^T c,$20 with $u[n] = x[n] + x[n] g_n^T c,$21, variables are reordered so that the late set $u[n] = x[n] + x[n] g_n^T c,$22 is least significant. The algorithm then tries free-set sizes $u[n] = x[n] + x[n] g_n^T c,$23 from $u[n] = x[n] + x[n] g_n^T c,$24 upward, enumerates supersets $u[n] = x[n] + x[n] g_n^T c,$25, computes $u[n] = x[n] + x[n] g_n^T c,$26 by scanning cofactors in the truth table, and accepts a solution if $u[n] = x[n] + x[n] g_n^T c,$27 and $u[n] = x[n] + x[n] g_n^T c,$28. The area is estimated pessimistically as

$u[n] = x[n] + x[n] g_n^T c,$29

with exact support-minimizing encoding deferred to the final cover. Candidate enumeration is reduced from $u[n] = x[n] + x[n] g_n^T c,$30 to $u[n] = x[n] + x[n] g_n^T c,$31 by symmetry, and for $u[n] = x[n] + x[n] g_n^T c,$32 the method restricts to $u[n] = x[n] + x[n] g_n^T c,$33 candidates without don’t-cares to cap runtime (Calvino et al., 2024).

The empirical results quantify the delay-shaping effect. On heavily optimized EPFL combinational benchmarks mapped to 6-LUTs, on-the-fly ACD reduces logical depth by 7.52% on average relative to standard delay-driven mapping with structural choices, with temporary increases of 8.13% in LUTs and 7.87% in edges. A second mapping round using the ACD result as structural choices yields an average delay improvement of 12.39% and an area reduction of 2.20%, with edges roughly unchanged. The paper also reports that the method improves 4 of the best delay results in the EPFL synthesis competition without using design-space exploration (Calvino et al., 2024).

In this literature, the LUT is not a stored table of filter coefficients or nonlinear control points. It is the target implementation primitive itself, and “delay shaping” means steering critical signals through a shallower structural realization.

6. Comparative properties, trade-offs, and limitations

Across the three domains, LUT-assisted delay shaping is consistently a complexity-management strategy, but the relevant trade-offs are domain specific.

In DPD, the principal trade-off is between modeling flexibility and processing cost. The paper explicitly recommends SPH for modest memory effects, relaxed ACLR targets, and minimal complexity, and SMP when stronger delay-selective memory is present or when performance close to MP is required. It also states that SMP and SPH use single-envelope indexing $u[n] = x[n] + x[n] g_n^T c,$34, which may not capture some dynamic or cross-term effects addressed by GMP, and that extremely long-term memory may require larger $u[n] = x[n] + x[n] g_n^T c,$35 or augmented structures. For extreme linearization targets, MP or GMP may marginally outperform SMP, but at significantly higher complexity (Campo et al., 2019).

In delay–Doppler pulse-shaping, the trade-off is between boundary smoothness, OOB suppression, BER behavior, and implementation burden. Circular pulse-shaping is efficient and compatible with FFT-based implementations, but suffers from wrap-around and high OOB unless ZGs are inserted. Linear pulse-shaping preserves smooth transients and has inherently lower OOB, but requires overlap-and-add and pulse truncation. ODDM adds Doppler-dependent filtering, which produces the staircase PSD and increases LUT size to $u[n] = x[n] + x[n] g_n^T c,$36, though the paper characterizes the resulting memory footprint as modest for $u[n] = x[n] + x[n] g_n^T c,$37 and $u[n] = x[n] + x[n] g_n^T c,$38, namely about 1056 complex entries (Bayat et al., 2023).

In delay-driven logic synthesis, the dominant trade-offs are delay versus area and runtime versus decomposition flexibility. On-the-fly ACD is intentionally delay oriented; area can increase temporarily because additional BS LUTs are introduced, although area-recovery passes or remapping can recover and even improve area. The benefits are strongest when non-$u[n] = x[n] + x[n] g_n^T c,$39-feasible cuts lie on or near the critical path. The paper also notes that strict two-level decompositions become harder as $u[n] = x[n] + x[n] g_n^T c,$40 grows or as more inputs are simultaneously late, unless more BS functions are allowed. Its delay model ignores interconnect, so placement- or congestion-aware variants are identified as a possible further improvement in correlation with post-place-and-route timing (Calvino et al., 2024).

A recurring misconception would be to assume that the “delay” in all three cases denotes the same object. The cited works indicate otherwise. In DPD, delay is physical memory in a nonlinear dynamical system; in delay–Doppler modulation, it is a transform-domain axis along which pulse-shaping is applied; in FPGA mapping, it is logical path depth under LUT constraints. A plausible implication is that cross-domain transfer of terminology is useful only at the level of abstraction—compact LUT-mediated control of delay-sensitive structure—not at the level of algorithmic details or performance metrics.

Another common point is that each domain uses LUTs to avoid a more expensive direct representation. Spline-LUT DPD avoids high-order polynomial bases and basis orthogonalization; delay–Doppler LUT implementations avoid repeated generation and modulation of shaping kernels; and on-the-fly ACD avoids full encoding during evaluation by relying on multiplicity tests and delayed construction of support-minimized BS functions. This suggests a broader design principle: LUT assistance becomes especially effective when the expensive part of the problem can be isolated into a compact function representation whose delay behavior is then separately optimized (Campo et al., 2019, Bayat et al., 2023, Calvino et al., 2024).