Phase Resolution Circuit Overview

• Phase Resolution Circuits are a family of designs that generate, select, discriminate, or measure phase with controlled granularity, applicable in timing ASICs, RF detectors, and quantum circuits.
• These circuits employ various implementations—such as DLL-based CMOS shifters, reflective and transmission-type phasers, and digital correction engines—to achieve precise phase or group delay resolution even amid practical nonidealities.
• Their applications span high-resolution timing for particle detectors, phase ambiguity removal in RF systems, and the restoration of computational exactness in reversible and quantum circuit designs.

In the cited literature, a phase resolution circuit is not a single standardized device class but a family of circuits whose central function is to generate, select, discriminate, measure, or computationally resolve phase with controlled granularity or ambiguity removal. Depending on the domain, “resolution” denotes a time increment in clock alignment, a group-delay swing in Radio Analog Signal Processing (R-ASP), an unambiguous angular detection range in RF instrumentation, a noise floor in digital phase metrology, or the removal of residual relative phase in reversible and quantum logic. Representative formulations span DLL-based CMOS phase shifters for detector ASICs, reflective and transmission-type phasers, switched I/Q detector cells, FPGA correction engines, resonant and photonic phase transducers, superconducting single-bit phase discriminators, and Clifford+$T$ constructions that implement functions “up to phase” and then restore exact computational outputs (Huang et al., 2023, Zou et al., 2014, Pérez et al., 2024, Amy et al., 2021).

1. Terminological scope and resolution metrics

The principal meanings of “phase resolution” in the cited work are heterogeneous.

Domain	Circuit role	Resolution notion
Timing ASICs	Clock phase selection and alignment	$97.7\,\mathrm{ps}$ LSB over $25\,\mathrm{ns}$ (Huang et al., 2023)
R-ASP phasers	Engineered $\phi(\omega)$ or $\tau(\omega)$	$\Delta\tau$ or $\sigma=\Delta\tau\cdot\Delta\omega$ (Zou et al., 2014)
RF phase detectors	Ambiguity-free phase discrimination	$360^\circ$ or $\pm180^\circ$ unambiguous range (Pérez et al., 2024)
PLL/DLL front ends	Phase/frequency comparison	Dead zone and blind zone (Challagundla et al., 23 Aug 2025)
Digital metrology	Phase extraction from sampled sinusoids	Noise floor or uncertainty (Kokuyama et al., 2016, Pogliano et al., 2011)
Reversible circuits	Elimination of residual diagonal phases	Exactness after matched uncompute or measurement-assisted correction (Amy et al., 2021)

This distribution suggests that the phrase functions as a cross-domain descriptor rather than a narrow taxonomy. The common thread is not a specific topology, but the controlled mapping between a physical or logical phase variable and a usable output: a shifted clock edge, a dispersed spectrum, a DC detector voltage pair, a corrected FPGA sum vector, a resonator state, or a computational-basis state.

A further distinction in the literature is between phase and group delay. In microwave phasers, the operative quantity is often $\tau(\omega)=-d\phi(\omega)/d\omega$, and “resolution” is associated with delay swing rather than instantaneous phase angle. By contrast, clock shifters, RF detector cells, and FPGA phase meters work directly with phase offset in time or angle.

2. Clock-domain phase selection and timing alignment

A concrete timing-domain phase resolution circuit is the high-resolution clock phase shifter implemented for the ALTIROC2 read-out ASIC for the ATLAS High-Granularity Timing Detector. In this design, the on-chip PLL provides $97.7\,\mathrm{ps}$0 and $97.7\,\mathrm{ps}$1 references, and the phase-shifter block supplies two independent $97.7\,\mathrm{ps}$2 clocks, one $97.7\,\mathrm{ps}$3 clock, and two $97.7\,\mathrm{ps}$4 clocks, each adjustable over a full $97.7\,\mathrm{ps}$5 range with approximately $97.7\,\mathrm{ps}$6 steps. The architecture combines a coarse-phase unit with $97.7\,\mathrm{ps}$7 steps of $97.7\,\mathrm{ps}$8 and a fine-phase unit in which a $97.7\,\mathrm{ps}$9 DLL subdivides one $25\,\mathrm{ns}$0 period into $25\,\mathrm{ns}$1 taps, so that $25\,\mathrm{ns}$2. A re-sampler aligns the three lower-frequency outputs onto a fine-shifted $25\,\mathrm{ns}$3 edge to maintain uniform granularity across all outputs (Huang et al., 2023).

The circuit-level implementation is notable for how phase resolution is preserved under practical constraints. The coarse path uses two D-flip-flops as a differentiator generating a narrow pulse every $25\,\mathrm{ns}$4, asynchronously reloading two $25\,\mathrm{ns}$5-bit counters to prevent single-event-upset accumulation. The fine path uses a VCDL of $25\,\mathrm{ns}$6 identical cells yielding $25\,\mathrm{ns}$7 uniform taps, a classic DLL loop of phase detector, charge pump, first-order LPF, and VCDL, and two identical hierarchical $25\,\mathrm{ns}$8-to-$25\,\mathrm{ns}$9 muxes built from symmetric transmission-gate cells. A metastability-safe resampling scheme pre-samples each low-frequency clock by a DFF clocked by the fine-shifted $\phi(\omega)$0 output and selects between raw and pre-sampled versions through a “metastability predictor” that scans across the $\phi(\omega)$1 fine taps (Huang et al., 2023).

Measured results place the circuit squarely in the class of high-resolution timing-alignment hardware. Fabricated in a $\phi(\omega)$2 CMOS process, it occupies $\phi(\omega)$3, provides $\phi(\omega)$4 steps over $\phi(\omega)$5, exhibits DNL of $\phi(\omega)$6 and INL of $\phi(\omega)$7, and shows RMS jitter below $\phi(\omega)$8 over $\phi(\omega)$9 to $\tau(\omega)$0 including the upstream PLL and FPGA source. Power is $\tau(\omega)$1, and phase noise is unchanged up to $\tau(\omega)$2 TID. In context, this circuit is a key enabler of the ALTIROC requirement for per-channel timing alignment with better than $\tau(\omega)$3 granularity and of the HGTD front-end goal of per-hit timing near $\tau(\omega)$4 (Huang et al., 2023).

3. Group-delay phasers and true phase-shifting networks

In R-ASP, a phase resolution circuit is typically a phaser: a one-port or two-port network whose phase response $\tau(\omega)$5 is tailored so that its group delay $\tau(\omega)$6 follows a prescribed law. The cited literature treats the delay swing $\tau(\omega)$7 and, in one formulation, the product $\tau(\omega)$8 as the operative resolution metric because larger dispersion yields finer time-frequency discrimination (Zou et al., 2014).

The planar reflective phaser based on open-ended edge-coupled lines provides a canonical synthesis route. It cascades $\tau(\omega)$9 half-wavelength resonators in a planar side-coupled topology, maps the target bandpass phase law to a lowpass variable, constructs a Hurwitz polynomial $\Delta\tau$0 such that $\Delta\tau$1, extracts a normalized lowpass prototype, converts it to bandpass admittance inverters $\Delta\tau$2, and then converts the resulting even- and odd-mode impedances to physical widths, gaps, and lengths. The reported design is a $\Delta\tau$3th-order microstrip reflective phaser with a $\Delta\tau$4 group-delay swing over $\Delta\tau$5–$\Delta\tau$6, corresponding to $\Delta\tau$7, and measurement shows group delay rising linearly from approximately $\Delta\tau$8 at $\Delta\tau$9 to approximately $\sigma=\Delta\tau\cdot\Delta\omega$0 at $\sigma=\Delta\tau\cdot\Delta\omega$1 (Zou et al., 2014).

A second line of work increases resolution by exploiting reflection-type resonators and hybrid loading. The hybrid-cascade coupled-line phaser achieves roughly a $\sigma=\Delta\tau\cdot\Delta\omega$2–$\sigma=\Delta\tau\cdot\Delta\omega$3 larger $\sigma=\Delta\tau\cdot\Delta\omega$4 around each peak than a simple serial cascade of C-sections for the same maximum coupling and total unfolded length, and a four-unit HC design was used to approximate a linear $\sigma=\Delta\tau\cdot\Delta\omega$5 with $\sigma=\Delta\tau\cdot\Delta\omega$6 over $\sigma=\Delta\tau\cdot\Delta\omega$7–$\sigma=\Delta\tau\cdot\Delta\omega$8 under $\sigma=\Delta\tau\cdot\Delta\omega$9 (Paradis et al., 2014). Relatedly, a transmission-type phaser assembled from reflection-type units uses a broadband hybrid coupler to combine two identical RT phasers so that the composite device remains matched and two-port while inheriting the larger RT group-delay swing. The demonstrated implementation exhibits a $360^\circ$0 group-delay swing over a fractional bandwidth of about $360^\circ$1 around $360^\circ$2 (Zou et al., 2014).

A distinct but adjacent problem is the realization of a true phase shifter rather than a time delayer. The multi-pole multi-zero frequency-independent phase-shifter addresses the requirement $360^\circ$3 over multiple decades by cascading first-order lead/lag stages with transfer function

$360^\circ$4

so that the total phase is the sum of stage contributions $360^\circ$5. Measured examples include a two-stage network with $360^\circ$6 over $360^\circ$7–$360^\circ$8 and a five-stage network with $360^\circ$9 over $\pm180^\circ$0–$\pm180^\circ$1; gain can be flattened to within a few percent by frequency-dependent optimization of a single resistance (Bitar et al., 2013).

The same section of the literature also separates constant phase behavior from fixed-component intuition. The constant phase element work shows that a capacitive CPE or inductive CPE can be reproduced exactly, for impulse and step responses, by simple time-varying RL or RC circuits in which $\pm180^\circ$2 or $\pm180^\circ$3. This is not a group-delay phaser in the R-ASP sense, but it establishes another formal route by which circuit structure can enforce a prescribed phase law over frequency or time (Holm et al., 2020).

4. Phase detectors and digital measurement architectures

A large class of phase resolution circuits resolves ambiguity or suppresses systematic phase error in measurement systems. The switched dual-multiplier $\pm180^\circ$4 detector cell begins from the limitation of a conventional analog phase detector, where $\pm180^\circ$5 and inversion through $\pm180^\circ$6 restricts the unambiguous range to $\pm180^\circ$7. The proposed architecture time-multiplexes two measurements,

$\pm180^\circ$8

and then uses sign and magnitude tests with four calibrated straight-line sector fits to recover a unique $\pm180^\circ$9. Implemented with Murata QCS-592 hybrid couplers, MA4EX600L mixers, an RF switch, and a PICAXE microcontroller with $\tau(\omega)=-d\phi(\omega)/d\omega$0 memory, it measures over $\tau(\omega)=-d\phi(\omega)/d\omega$1–$\tau(\omega)=-d\phi(\omega)/d\omega$2, achieves $\tau(\omega)=-d\phi(\omega)/d\omega$3 ($\tau(\omega)=-d\phi(\omega)/d\omega$4) unambiguous detection, shows at $\tau(\omega)=-d\phi(\omega)/d\omega$5 a measured maximum phase error of $\tau(\omega)=-d\phi(\omega)/d\omega$6 in the balanced case and $\tau(\omega)=-d\phi(\omega)/d\omega$7 in the deliberately unbalanced case, and completes each measurement in less than $\tau(\omega)=-d\phi(\omega)/d\omega$8 (Pérez et al., 2024).

In PLL and DLL front ends, the main phase-resolution bottlenecks are dead zones and blind zones. The TSPC-based low-power CMOS PFD replaces conventional reset-heavy topologies with two dynamic True Single-Phase Clock flip-flops that self-reset during the low phase. The resulting detector eliminates the blind zone entirely and reduces the dead zone to $\tau(\omega)=-d\phi(\omega)/d\omega$9, with minimum detectable phase difference and timing resolution both about $97.7\,\mathrm{ps}$00. Implemented in TSMC $97.7\,\mathrm{ps}$01 CMOS, it uses $97.7\,\mathrm{ps}$02 transistors, occupies $97.7\,\mathrm{ps}$03, operates up to $97.7\,\mathrm{ps}$04, and consumes $97.7\,\mathrm{ps}$05 at $97.7\,\mathrm{ps}$06 input frequency (Challagundla et al., 23 Aug 2025).

Digital compensation engines address a different failure mode: phase errors induced by channel mismatch. Gao et al. describe a fully digital beam position and phase measurement system in which four under-sampled $97.7\,\mathrm{ps}$07 BPM channels are interpreted as digital I/Q streams, then individually pre-rotated by a $97.7\,\mathrm{ps}$08 rotation matrix that cancels each channel’s delay error $97.7\,\mathrm{ps}$09 and rescaled by $97.7\,\mathrm{ps}$10 before summation. The corrected beam phase is extracted as

$97.7\,\mathrm{ps}$11

Because both gain and phase corrections depend only on the attenuator setting, one-dimensional LUTs per channel suffice. Implemented in a Xilinx Virtex-5 FPGA, the pipeline latency is $97.7\,\mathrm{ps}$12, and phase correction precision better than $97.7\,\mathrm{ps}$13 is achieved over the dynamic range from $97.7\,\mathrm{ps}$14 to $97.7\,\mathrm{ps}$15 (Gao et al., 2019).

Kokuyama et al. address high-resolution heterodyne phase metering with a different digital strategy: modified fringe counting combined with two-sample zero-crossing interpolation. Over a block of $97.7\,\mathrm{ps}$16 ADC samples, integer half-cycle counts and fractional crossing positions are accumulated to form a phase-difference estimate at a constant-rate output, with low FPGA complexity and sub-$97.7\,\mathrm{ps}$17 latency. Demonstrated results include a floor noise of $97.7\,\mathrm{ps}$18 above approximately $97.7\,\mathrm{ps}$19 in an electrical test and $97.7\,\mathrm{ps}$20 from $97.7\,\mathrm{ps}$21 to $97.7\,\mathrm{ps}$22 when used with a commercial heterodyne interferometer (Kokuyama et al., 2016).

At the precision-metrology end, the INRIM wideband digital phase comparator uses symmetric active guarded transformers, synchronous digitization, asynchronous burst acquisition, offline iterative sine fitting, and an inversion procedure that swaps shunts to cancel channel bias. It is intended for comparing high-current shunts from several hundred milliamperes up to $97.7\,\mathrm{ps}$23 over $97.7\,\mathrm{ps}$24 to $97.7\,\mathrm{ps}$25, and the reported expanded uncertainty is less than $97.7\,\mathrm{ps}$26 for frequency up to $97.7\,\mathrm{ps}$27 in the measurement of the phase difference of a group of $97.7\,\mathrm{ps}$28 shunts (Pogliano et al., 2011).

5. Resonant, photonic, and superconducting implementations

Integrated and resonant platforms introduce an additional design requirement: phase control must often be maintained in the presence of amplitude distortion, resonator loss, or mode conversion. The integrated microwave-photonic circuit for filtering and phase shifting demonstrates a single Si$97.7\,\mathrm{ps}$29N$97.7\,\mathrm{ps}$30 TriPleX PIC that can be configured as either a tunable notch filter or a continuously tunable phase shifter. In phase-shifter mode, multi-order optical-sideband shaping and an on-chip linearization condition enforce a continuously tunable $97.7\,\mathrm{ps}$31 RF phase shift over $97.7\,\mathrm{ps}$32–$97.7\,\mathrm{ps}$33 with amplitude ripple below $97.7\,\mathrm{ps}$34. The measured link gain is $97.7\,\mathrm{ps}$35, the noise figure is $97.7\,\mathrm{ps}$36, and a two-tone test at $97.7\,\mathrm{ps}$37 improves SFDR from approximately $97.7\,\mathrm{ps}$38 without linearization to $97.7\,\mathrm{ps}$39 with on-chip linearization. The phase resolution is described as effectively continuous, limited by heater DAC resolution, with thermal tuning on the millisecond scale (Liu et al., 2023).

A room-temperature discrete resonant implementation appears in the capacitance-to-phase transducer of van Kann and Veryaskin. Here, a grounded sensing capacitor is placed in series with a moderate-$97.7\,\mathrm{ps}$40 resonant tank and then embedded in a modified all-pass architecture so that small changes in capacitance are converted into large phase shifts of a carrier while amplitude-modulation errors are suppressed. For $97.7\,\mathrm{ps}$41 and $97.7\,\mathrm{ps}$42, the resonant frequency is approximately $97.7\,\mathrm{ps}$43, the measured sensitivity is approximately $97.7\,\mathrm{ps}$44, the relative capacitance resolution is equal to or better than $97.7\,\mathrm{ps}$45 in a $97.7\,\mathrm{ps}$46 bandwidth, and the predicted displacement noise is approximately $97.7\,\mathrm{ps}$47 (Kann et al., 2023).

The Josephson Digital Phase Detector realizes a more radical mapping from analog phase to digital state. Its flux-switchable superconducting potential is tuned from a single-well to a double-well form so that the sign of the phase quadrature of a coherent input tone determines relaxation into one of two classical states, $97.7\,\mathrm{ps}$48 or $97.7\,\mathrm{ps}$49. Measurements demonstrate operation up to $97.7\,\mathrm{ps}$50 input tones, and when the drive amplitude satisfies $97.7\,\mathrm{ps}$51, the step-like occupation-probability curve has error below $97.7\,\mathrm{ps}$52, corresponding to fidelity of at least $97.7\,\mathrm{ps}$53. Simulations for a $97.7\,\mathrm{ps}$54 tone with $97.7\,\mathrm{ps}$55 and $97.7\,\mathrm{ps}$56 yield more than $97.7\,\mathrm{ps}$57 fidelity (Palma et al., 2023).

A later photonic synthesis replaces amplitude equalization by topological design. The pole-zero winding method treats the scattering coefficient as a meromorphic function of complex frequency and uses Cauchy’s Argument Principle,

$97.7\,\mathrm{ps}$58

to guarantee an exact $97.7\,\mathrm{ps}$59 phase sweep when a scattering zero winds once around the operating point while the pole remains outside the contour. Imposing $97.7\,\mathrm{ps}$60 constrains the trajectory to an Apollonius circle, so constant amplitude and exact phase accumulation follow simultaneously by construction. This proposal targets integrated resonant modulators, programmable photonic circuits, and quantum or beam-steering interferometers that require amplitude-flat phase shifts (Krasnok, 24 Dec 2025).

6. Cross-domain distinctions and recurrent design constraints

Several distinctions recur across otherwise unrelated implementations. First, a phase shifter is not necessarily a time delayer: a delay line produces $97.7\,\mathrm{ps}$61, whereas a true phase shifter seeks $97.7\,\mathrm{ps}$62 over the design band (Bitar et al., 2013). Second, group-delay resolution and phase-angle resolution are not interchangeable: R-ASP phasers maximize $97.7\,\mathrm{ps}$63 or $97.7\,\mathrm{ps}$64, whereas detector cells and FPGA meters are judged by angular ambiguity, jitter, noise floor, or correction error (Zou et al., 2014).

Third, full-circle phase detection does not follow from a single sinusoidal detector characteristic. The single-multiplier law $97.7\,\mathrm{ps}$65 is intrinsically ambiguous beyond $97.7\,\mathrm{ps}$66, which is why the switched dual-multiplier detector must acquire both sine and cosine projections and then perform quadrant disambiguation (Pérez et al., 2024). Fourth, amplitude-flat phase shift is generally nontrivial: resonant phase shifters ordinarily mix amplitude and phase, and the cited solutions therefore rely on modified all-pass constructions, multi-order sideband shaping with IMD3 cancellation, or explicit pole-zero trajectories on iso-$97.7\,\mathrm{ps}$67 contours (Kann et al., 2023, Liu et al., 2023, Krasnok, 24 Dec 2025).

Fifth, high resolution is repeatedly limited by practical nonidealities rather than the nominal transfer law alone. In the ALTIROC clock shifter, matched delay-cell layout, symmetric mux trees, a first-order loop filter, and a metastability-safe resampler are used to control DNL, INL, jitter, and glitching (Huang et al., 2023). In the TSPC-PFD, the dead zone is set by the TSPC latch’s minimum precharge-to-evaluate delay (Challagundla et al., 23 Aug 2025). In FPGA and metrology systems, phase errors track attenuator state, ADC timing skew, cable mismatch, hybrid phase deviation, or amplitude imbalance, and calibration or inversion becomes part of the phase-resolution mechanism rather than an external accessory (Gao et al., 2019, Pogliano et al., 2011).

These regularities suggest a general design rule: increasing phase resolution usually requires a second mechanism that stabilizes the mapping from phase to output under nonideal conditions. Depending on the field, that second mechanism is a DLL, a matched compute/uncompute pair, a calibration LUT, a hybrid coupler, an all-pass embedding, a flux pulse, or a topologically constrained control loop.

7. Phase resolution in reversible and quantum circuit design

In reversible and quantum circuit design, “phase resolution” denotes neither timing granularity nor RF angle readout. The relevant problem is that a classical function may be implemented up to phase, after which the residual diagonal phase must be canceled coherently or removed by measurement and feed-forward. The formal duality is induced by Hadamard conjugation,

$97.7\,\mathrm{ps}$68

which converts a computational-basis XOR action into a diagonal phase oracle. A unitary $97.7\,\mathrm{ps}$69 implements $97.7\,\mathrm{ps}$70 up to phase when $97.7\,\mathrm{ps}$71 for some diagonal $97.7\,\mathrm{ps}$72, with $97.7\,\mathrm{ps}$73 the permutation corresponding to the classical oracle (Amy et al., 2021).

This framework systematizes two major circuit families. Relative-phase circuits reduce $97.7\,\mathrm{ps}$74-count by allowing a controlled logical action to accumulate benign phase factors. Examples include Selinger’s doubly-controlled $97.7\,\mathrm{ps}$75 gate with $97.7\,\mathrm{ps}$76-count $97.7\,\mathrm{ps}$77 versus $97.7\,\mathrm{ps}$78-count $97.7\,\mathrm{ps}$79 for an exact ancilla-free Toffoli, Giles–Selinger’s $97.7\,\mathrm{ps}$80-controlled $97.7\,\mathrm{ps}$81 with $97.7\,\mathrm{ps}$82-count $97.7\,\mathrm{ps}$83, and Maslov’s $97.7\,\mathrm{ps}$84-qubit Toffoli up to phase with $97.7\,\mathrm{ps}$85-count $97.7\,\mathrm{ps}$86. Measurement-assisted terminations remove temporary values without explicit uncomputation by applying $97.7\,\mathrm{ps}$87, measuring in the $97.7\,\mathrm{ps}$88 basis, and using classical feed-forward such as controlled-$97.7\,\mathrm{ps}$89 or controlled-$97.7\,\mathrm{ps}$90 to restore exactness; Gidney’s temporary logical-AND thereby separates initialization in $97.7\,\mathrm{ps}$91-count $97.7\,\mathrm{ps}$92 from termination in $97.7\,\mathrm{ps}$93-count $97.7\,\mathrm{ps}$94 (Amy et al., 2021).

The act of “resolving” phase is therefore the restoration of a correct classical reversible map from an implementation that temporarily exploited the phase basis for lower resource cost. Matched compute/phase-shift/uncompute patterns ensure that diagonal phases commute into cancellation, while measurement-assisted cleanup uses measurement collapse plus small classical corrections. The paper explicitly characterizes a “phase resolution circuit” as any composite that encodes part of a Boolean computation into a diagonal phase unitary for $97.7\,\mathrm{ps}$95-economy and then resolves that diagonal into correct computational-basis information without leaving an uncontrolled residual phase (Amy et al., 2021). In this usage, the term shares with analog phase-resolution circuits the theme of ambiguity removal, but the resolved quantity is logical exactness rather than a continuous phase variable.