ThermoDSE: Thermal-Aware DNN Accelerator DSE

• ThermoDSE is a thermal-aware design space exploration framework for chiplet-based DNN accelerators that jointly optimizes chiplet partitioning, core granularity, and task orchestration under thermal and area constraints.
• The framework employs an Energy-Delay-Inverse-Yield metric and integrates HotSpot 6.0 thermal estimation with TED initialization and SCBO-based constrained Bayesian optimization to efficiently navigate up to a billion design configurations.
• It demonstrates significant improvements over baseline methods by achieving up to 3.5× lower EDYP, faster convergence, and a comprehensive treatment of inter-chiplet communication and yield, making it a pivotal tool for early-stage accelerator design.

Searching arXiv for papers on ThermoDSE and closely related chiplet-based DNN accelerator DSE frameworks. ThermoDSE is a thermal-aware and comprehensive design space exploration framework for chiplet-based DNN accelerators, introduced to optimize architecture design, task orchestration, and inter-chiplet communication under strict thermal and area constraints. It targets early-stage exploration of chiplet-based accelerators in which chiplet granularity, core granularity, fine-grained task modeling, inter-chiplet spacing, NoC/NoP communication, and die yield must be considered jointly rather than in isolation. The framework defines its objective with the Energy-Delay-Inverse-Yield product, $EDYP = E \times D \times Y^{-1}$, and uses HotSpot 6.0 for thermal estimation together with a simulation-and-optimization loop based on TED initialization and SCBO-based constrained Bayesian optimization (Peng et al., 8 Jul 2026).

1. Origin, scope, and problem formulation

ThermoDSE was proposed in the context of chiplet-based DNN accelerators, which the paper characterizes as a scalable path for balancing performance and yield for modern AI workloads while facing critical area and thermal constraints. Its stated motivation is that prior approaches did not jointly account for thermal constraints, interposer or package area constraints, chiplet granularity, core granularity, fine-grained task orchestration, and inter-chiplet communication with data reuse. The authors explicitly describe ThermoDSE as “the first framework that involves all these factors,” qualifying the statement with “to the best of our knowledge” (Peng et al., 8 Jul 2026).

The framework is centered on a constrained optimization problem over a design space $\Omega$: $$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$ where $x$ is a candidate design, $c_1(x)$ is peak temperature, $C_1$ is the temperature limit, $c_2(x)$ is interposer area, and $C_2$ is the area limit. The objective is

$EDYP = E \times D \times Y^{-1}$

with $E$ denoting total energy, $\Omega$0 total delay, and $\Omega$1 die yield.

The paper motivates thermal awareness with workload-dependent hotspot behavior on a Simba-like system. Reported peak temperatures are $\Omega$2 for GoogLeNet, $\Omega$3 for BERT, and $\Omega$4 for an AR/VR multi-DNN workload. These examples are used to argue that thermal behavior depends not only on hardware configuration but also on workload characteristics such as computation density, activation sparsity, and communication intensity. The same discussion is used to reject a purely runtime-DVFS response for the targeted edge and mobile scenario, where the paper assumes sequential execution of multiple DNNs (Peng et al., 8 Jul 2026).

2. Architectural model and explored design space

ThermoDSE assumes a Simba-like chiplet-based accelerator architecture composed of compute chiplets, an I/O chiplet, an intra-chiplet NoC, an inter-chiplet NoP, and DRAM attached through the I/O chiplet. Each compute chiplet contains multiple NPU cores. Each core includes a control unit, a communication unit, buffers, a matrix unit, and a vector unit. The matrix unit is a weight-stationary systolic array of size $\Omega$5, while the vector unit has $\Omega$6 compute units for elementwise, pooling, and normalization-style operations (Peng et al., 8 Jul 2026).

The on-core storage hierarchy includes a uniform buffer $\Omega$7, an IFM buffer $\Omega$8, a weight buffer $\Omega$9, an accumulator register file, and an OFM buffer. The paper states that IFM, weight, and OFM buffer capacities are fixed to one-fourth of the uniform buffer, following Simba- and DaVinci-style assumptions, and that all on-chip buffers except the uniform buffer are assumed to be double-buffered.

The design variables explored by ThermoDSE are explicitly enumerated in the paper.

Variable	Meaning	Range
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$0	DNN cores in X dimension	1–8
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$1	DNN cores in Y dimension	1–8
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$2	Chiplet partitions in X dimension	1–8
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$3	Chiplet partitions in Y dimension	1–8
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$4	Systolic array height	16–256, step 16
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$5	Systolic array width	16–256, step 16
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$6	Inter-chiplet spacing	0.5–3.5 mm, step 0.3 mm
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$7	Uniform buffer size	128–8192 KB, powers of two
$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$8	NoC/NoP bandwidth	16–256, step 16

The paper states that this design space can contain up to one billion points. Inter-chiplet spacing is treated as a first-class physical variable because it directly affects both interposer area and thermal isolation. This suggests that ThermoDSE treats chiplet partitioning not merely as an architectural abstraction but as a physically instantiated package-level decision.

Area is modeled at both die and package levels. The total area is written as

$$\underset{x\in \Omega}{\arg\min} \ EDYP(x) \quad \text{s.t.} \quad c_1(x) \leq C_1,\ c_2(x) \leq C_2$$9

and the compute-die area is

$x$0

The paper assumes auxiliary modules occupy about $x$1 of die area, following Chiplet-Gym. Yield is modeled with the negative-binomial expression

$x$2

where $x$3 is defect density and $x$4 is the clustering parameter (Peng et al., 8 Jul 2026).

3. Fine-grained task orchestration and performance modeling

A defining feature of ThermoDSE is its adoption of fine-grained task orchestration rather than network-level parallelism. The workload is represented as a microtask graph

$x$5

with node set

$x$6

and edge set

$x$7

Each microtask therefore corresponds to a tile of a layer output with explicit index ranges over spatial and channel dimensions.

The orchestration flow consists of four stages: layer partitioning, microtask DAG generation, scheduling, and mapping. Layers at the same depth are initially partitioned into $x$8 microtasks, where $x$9 is the number of DNN cores. A layer’s microtask count $c_1(x)$0 is proportional to its computational load relative to the total workload of that depth, and $c_1(x)$1 is increased if the uniform buffer cannot hold the microtask. For CONV and GEMM, the partition priorities are given as $c_1(x)$2 for CONV and $c_1(x)$3 for GEMM (Peng et al., 8 Jul 2026).

Scheduling uses DP-based iterative scheduling. The stated priorities are to schedule microtasks from the same layer first in order to maximize IFM and weight reuse, then to prioritize tasks at the same depth to release shared data earlier, and finally to fill remaining idle cores with later-depth ready tasks whose dependencies are already satisfied. Mapping is explicitly thermal-aware: because center cores accumulate more lateral heat than corner cores, the highest-power microtasks are assigned first to corner cores, while lower-power tasks are assigned to center cores.

The latency model is hierarchical. Total latency is

$c_1(x)$4

with per-workload latency

$c_1(x)$5

and per-round latency

$c_1(x)$6

where the round completes when the slowest core finishes. For one core,

$c_1(x)$7

Communication delay is modeled as

$c_1(x)$8

The paper states that NoC/NoP delay is determined by the most congested link and gives a corrupted printed expression that is clearly intended to mean a volume-over-bandwidth model for the most congested link.

Core execution delay comprises computation and on-chip data movement. The printed equation is

$c_1(x)$9

while the subsequent equation defines

$C_1$0

in reconstructed form from the surrounding text. The computation term is

$C_1$1

where the utilization factors account for padding losses when tensor dimensions do not align with systolic-array dimensions.

Energy is modeled as

$C_1$2

with

$C_1$3

The paper also uses the generic relation

$C_1$4

for operation-level energy accounting. Average module power for thermal analysis is written as

$C_1$5

which the paper uses together with component floorplans as HotSpot inputs (Peng et al., 8 Jul 2026).

4. Thermal model and thermal-aware optimization loop

ThermoDSE performs thermal estimation with HotSpot 6.0. The thermal stack includes compute dies, an interposer carrying the NoP, thermal interface material, a heat spreader, and a heat sink. NoP power is distributed spatially on the interposer, and material parameters for TIM, spreader, and sink are taken from TESA according to the paper. Thermal feasibility is determined by the peak-temperature constraint $C_1$6, and the main experiments use a $C_1$7 temperature limit, $C_1$8 ambient temperature, and $C_1$9 convection resistance (Peng et al., 8 Jul 2026).

The framework’s optimization loop has two stages. Initialization is performed by Transductive Experimental Design, or TED, which is used to choose representative and diverse initial samples from the design space. The main optimization stage uses SCBO, a constrained Bayesian optimization method with trust regions. Gaussian-process surrogate models are fitted for both the objective and the constraints, using a scaled Matérn kernel. The trust-region length $c_2(x)$0 is updated according to success or failure counters: $c_2(x)$1 and candidate points are selected with constrained maximum posterior sampling. If feasible posterior samples exist in the trust region, the method chooses the one with minimum sampled objective; otherwise it chooses the point with minimum total constraint violation.

This trust-region strategy is important because the paper repeatedly argues that the best designs tend to lie near the thermal and area boundaries rather than deep inside the feasible region. A related threshold-sensitivity study shows that a smaller threshold, $c_2(x)$2, finds feasible designs quickly but produces worse final EDYP, while a larger threshold, $c_2(x)$3, finds near-optimal designs in about 725 iterations after slower exploration. This behavior is presented as evidence that boundary-aware constrained exploration is central to the problem structure (Peng et al., 8 Jul 2026).

5. Experimental methodology and reported results

ThermoDSE is evaluated on a server equipped with an Intel Xeon Gold 6246R at 3.40 GHz and 128 GB memory. MAC modules are synthesized in TSMC 28 nm and scaled to 14 nm with DeepScaleTool. The reported circuit parameters include 1.17 pJ/bit for D2D interconnect energy, 81K $c_2(x)$4 of D2D area per 25 Gb/s bandwidth, 0.6 pJ/bit for NoC energy, 8 pJ/bit for DRAM energy, and 1.8 GHz frequency. Yield parameters are $c_2(x)$5 and $c_2(x)$6 (Peng et al., 8 Jul 2026).

The benchmark suite targets AR/VR-style multi-DNN workloads and includes ResNet-50, GoogLeNet, MobileNetv2, Yolo-v2, U-Net, and BERT-Small. The architecture-level comparisons include a Simba-like baseline, TESA-like designs, a Chiplet-Gym-like design, and the ThermoDSE-optimized architecture.

Under a $c_2(x)$7 temperature constraint and a $c_2(x)$8 area constraint, ThermoDSE identifies a best design with 5×4 NPU cores, partitioned into 1×2 chiplets, inter-chiplet spacing of 2.3 mm, 240 GB/s NoC/NoP bandwidth, a 1024 KB uniform buffer, and a 208×112 systolic array. The reported metrics for this design are $c_2(x)$9 peak temperature, 59.8 mJ energy, 2.01 ms delay, 0.911 yield, and EDYP 132.2.

The Simba-like baseline is reported at $C_2$0, 103.3 mJ, 4.46 ms, 0.998 yield, and EDYP 461.6. Relative to that baseline, ThermoDSE reports 1.7× lower energy, 2.2× lower delay, and 3.4× lower EDYP. The abstract gives the broader claim that ThermoDSE achieves up to 3.5× improvement in Energy-Delay-Inverse-Yield compared with “state-of-the-art Simba and other baselines.” Against DSE algorithms, the abstract reports 3.7× and 29.4× runtime speedups relative to simulated annealing and reinforcement-learning-based methods, respectively, and Table VI reports convergence in 850 iterations for ThermoDSE, 3,180 iterations for simulated annealing, and 25,000 iterations for PPO-based RL (Peng et al., 8 Jul 2026).

The paper also emphasizes modeling fidelity. For the Chiplet-Gym-like baseline, the analytical model’s prediction is $C_2$1, 107.6 mJ, 4.07 ms, and EDYP 441.9, but after re-evaluation with ThermoDSE’s fine-grained modeling, the same design is reported at $C_2$2, 70.2 mJ, 2.35 ms, and EDYP 166.5. The paper summarizes these discrepancies as errors of $C_2$3, $C_2$4 in energy, and $C_2$5 in delay. This result is used to argue that simplified analytical models can be materially misleading for thermal and communication-sensitive chiplet accelerators.

An exhaustive local scan of about 440K neighboring designs around the ThermoDSE optimum finds a best feasible point that differs only slightly, chiefly by using 256 GB/s instead of 240 GB/s bandwidth. The paper presents this as evidence that ThermoDSE reaches an almost optimal region. It also reports a U-shaped EDYP trend as resources are increased: initial resource additions reduce delay and improve EDYP, but further increases raise communication energy while delay improvements saturate.

6. Interpretation, limits, and relation to adjacent frameworks

ThermoDSE’s core contribution lies in treating chiplet partitioning, core design, task orchestration, communication, area, temperature, and yield as a single constrained optimization problem rather than a sequence of separate decisions. The paper contrasts this position with TESA, which it characterizes as thermal-aware but limited to coarse-grained network-level parallelism without NoC/NoP communication or data reuse, and with Chiplet-Gym, which it characterizes as package-aware but driven by a simple analytical model that omits chiplet granularity exploration, core-level optimization, and fine-grained sharing behavior. The Simba-like system serves mainly as an architectural reference point rather than a full DSE methodology (Peng et al., 8 Jul 2026).

Several limitations are explicit. ThermoDSE targets 2.5D integration rather than 3D stacking. Thermal estimation is steady-state because it relies on HotSpot 6.0 rather than transient thermal simulation. The architecture template is Simba-like, with a weight-stationary systolic array and a vector unit, so the framework is not architecture-agnostic in a strong sense. Some parameters are fixed to limit optimization dimensionality. The thermal-aware mapping policy is greedy rather than globally optimal. The workload scenario emphasizes sequential multi-DNN execution for edge and mobile systems, and the yield model remains an analytical negative-binomial model rather than a foundry-specific one.

The paper’s area breakdown for the final $C_2$6 design reports about $C_2$7 of area devoted to computation units, a buffer-area share that is $C_2$8 less than compute-unit area, and $C_2$9 of chip area reserved for cooling structures. Under a tighter $EDYP = E \times D \times Y^{-1}$0 area budget, the paper reports a feasible design with 4×4 cores, 1×2 chiplets, 2.3 mm inter-chiplet spacing, 144×112 systolic dimensions, 1024 KB $EDYP = E \times D \times Y^{-1}$1, and 240 bandwidth, yielding 2.27 ms delay, 60 mJ energy, and 0.943 yield. The paper uses this to argue that area and thermal constraints become more tightly coupled as the package budget shrinks.

In that sense, ThermoDSE is best understood as a thermal-aware architecture-and-orchestration DSE framework for chiplet-based DNN accelerators, rather than a thermal checker appended to a conventional accelerator simulator. Its most distinctive technical identity is the joint use of fine-grained microtask modeling, HotSpot-based thermal estimation, and TED-plus-SCBO constrained optimization to search a design space that the paper states can reach one billion points (Peng et al., 8 Jul 2026).