Wafer-Scale Chips: Integration & Architecture

• Wafer-scale chips are monolithic integration devices spanning full wafers, embedding millions of cores, local memories, and high-speed interconnects.
• The paper details methodologies like reticle stitching, silicon interposer use, and dynamic fault isolation, achieving metrics such as 7.5 POPS and over 70% utilization.
• It highlights advances in computational models, programming tools, and heterogeneous integration that enable scalable AI, quantum, neuromorphic, and photonic processing.

Wafer-scale chips (WSCs) are monolithic or semi-monolithic integrated devices that span the entirety or a substantial fraction of a silicon wafer, embedding hundreds of thousands to millions of cores, local memories, routers, and high-speed interconnects. Unlike conventional chiplet-based designs—where individual dies are diced, packaged, and then interconnected—WSCs eliminate the need for chip boundaries and off-chip I/O, achieving unprecedented levels of integration density, bandwidth, and low-latency communication. Their emergence redefines what is computationally and architecturally possible across high-performance computing, AI/ML acceleration, quantum devices, neuromorphic processing, photonic platforms, and heterogeneous integration, rendering legacy Moore's Law scaling and traditional datacenter architectures increasingly obsolete (Hu et al., 2023).

1. Foundations and Architectural Paradigms

Wafer-scale integration (WSI) enables compute devices with >10,000 mm² active area, often realized through reticle stitching, high-density silicon interposers, or advanced redistribution layer (RDL) fan-out. Exemplars include the Cerebras CS-1/CS-2 (reticle stitch), Tesla Dojo (InFO-SoW), and large neuromorphic wafers such as BrainScaleS and DarwinWafer. At the architectural level, these chips typically instantiate a 2D mesh of independent compute tiles (“cores” or chiplets), each with private SRAM (tens of KB to MB), local routers for network-on-chip (NoC) connectivity, and per-core SIMD/FMA units for floating-point operations. Aggregate compute power on modern WSCs reaches several petaOPS (e.g., Cerebras CS-2: 7.5 POPS over 853K cores) (Hu et al., 2023).

On-wafer SRAM is either distributed per core or stacked as HBM chiplets, in aggregate reaching 40–70 GB (Cerebras WSE-2: 40 GB SRAM, 22 PB/s bandwidth; typical single-die DRAM: 64–96 GB, 1–2.5 TB/s per die) (Wang et al., 13 Dec 2025). Interconnect is implemented as a high-bandwidth, low-latency 2D mesh or, in advanced cases, folded 3D fabrics. Each router typically services four compass directions, supporting cycle-per-hop latency (~0.4 ns/tile @ 1.2 GHz), hardware-managed virtual channels, and point-to-point streaming. Wafer-to-board I/O leverages high-density microbumps, high-aspect-ratio TSVs, and fan-out redistribution (Zhu et al., 30 Aug 2025). Technological advances in electro-thermal closure and integrated warpage-tolerant assembly enable robust operation over 300 mm wafers (DarwinWafer) (Zhu et al., 30 Aug 2025).

2. Computational and Memory Models

WSCs are architected for memory-bandwidth-bound workloads, where the majority of data movement and computational bottlenecks arise within the chip rather than between discrete chips or the package. The event-driven programming model is predominant, utilizing hardware FIFOs and lock-free mechanisms. The arithmetic and byte-movement models for stencil computations on wafer-scale (e.g., BiCGStab on Cerebras CS-1) allocate work so that each tile can store problem-local data and Krylov vectors within its own SRAM. Bandwidth per tile typically reaches 24–28 GB/s, summing to 10+ PB/s for the entire wafer (Rocki et al., 2020).

The PLMR model—Partitionable cores (P), Latency (L), per-core Memory (M), and Routing resource (R)—guides kernel design for matrix multiplies and reductions, enforcing constraints so that all computation, memory footprints, and routing remain local or minimally-hopped. MeshGEMM and MeshGEMV are canonical PLMR-compliant primitives for GEMM/GEMV in LLM inference, demonstrating >70% utilization across 720×720 core meshes and >600× speedup and 22× energy efficiency vs. contemporary GPU clusters (He et al., 6 Feb 2025).

3. Integration Technologies and Yield Management

WSCs leverage reticle-stitching (Cerebras), silicon interposers (DarwinWafer, “chiplet-on-interposer”), and redistribution layer fan-out. Reticle stitching achieves true monolithic dies (e.g., CS-2: 46,255 mm²), but imposes strict process uniformity and redundancy for yield management—typically exp(exp(–D·A)), with D = defect density and A = area—favoring local redundancy at core/link level and dynamic compiler-guided blacklisting (Hu et al., 2023). Chiplet-on-interposer systems employ known-good-die (KGD) selection and bump assignment algorithms (e.g., DarwinWafer’s IBPlanner), yielding >80% system yield with multi-million IOs (Zhu et al., 30 Aug 2025).

For quantum and photonic wafers, robust Josephson junction fabrication achieves <3.5% global RSD in I_c and <1.8% local RSD on 1×1 cm areas via optimized resist treatment, dynamic oxidation, and uniform ashing (Kreikebaum et al., 2019). Semiconductor grafting enables wafer-scale heterogeneous integration of high-quality lattice-mismatched interfaces with >90% device yield and <3 nm thickness uniformity, fully compatible with CMOS back-end-of-line (Zhou et al., 12 Nov 2024).

4. Programming Models and Compiler Infrastructures

Programming WSCs requires explicit partitioning, placement, and routing of all tensor and data structures, due to the lack of global unified memory. System-level compilers (e.g., MACH) abstract execution by coordinating executive, response, and worker PEs in a hardware-agnostic “virtual machine” model. Memory liveness analysis, per-tile buffer reuse, and customized interconnect annotation are essential to fitting computation within tight SRAM budgets (e.g., 48 KB/tile in Cerebras CS-1; 1.25 MB/core in modern LLM wafers) (Essendelft et al., 18 Jun 2025).

Mapping strategies—whether for tensor parallelism, pipeline parallelism, or composite schemes—require traffic- and topology-aware optimization. Frameworks such as TEMP introduce tensor-stream partition (TSPP), bidirectional ring-based orchestration, and traffic-conscious mapping engines, minimizing contention and tail latency in 2D mesh networks for LLM training at wafer scale (Wang et al., 16 Dec 2025). Multi-fidelity Bayesian optimization and surrogate modeling (e.g., Theseus: cycle-accurate, GNN-based, and analytical NoC models) enable tractable exploration over tens of thousands of design candidates under area, power, and yield constraints (Zhu et al., 2 Jul 2024).

Expert parallelism for MoE models leverages mesh-aware placement (Entwined Ring Mapping), reducing all-to-all hop count and maximizing utilization, while non-invasive migration balancers amortize expert migration costs by utilizing complementary cold links and three-stage pipelining. These mechanisms yield >62% reduction in communication and up to 2.73× normalized MoE throughput versus GPU supernodes (Tang et al., 29 Oct 2025).

5. Application Domains: AI, Quantum, Neuromorphic, and Photonics

WSCs underpin AI inference and training workloads that stress memory bandwidth and on-chip compute, especially for LLMs, transformers, and expert-parallel MoEs. WaferLLM achieves up to 200× better accelerator utilization and 606× GEMV speedup over A100 GPUs on full LLM models, owing to full utilization of hundreds of thousands of cores and seamless mesh-based parallelism (He et al., 6 Feb 2025). LLM training frameworks (WATOS, TEMP) demonstrate 1.5–2.7× throughput and up to 1.9× power efficiency over the best GPU or previous wafer training strategies, with optimal configurations predicated on balancing DRAM, D2D bandwidth, and SRAM (Wang et al., 13 Dec 2025, Wang et al., 16 Dec 2025). Theseus finds Pareto-optimal points for throughput/power by dynamic fidelity switching; best results yield up to 73.7% performance and 42.4% power improvements versus early-generation WSCs (Zhu et al., 2 Jul 2024).

Quantum and neuromorphic domains exploit wafer-scale fabrication for large arrays of superconducting qubits (up to 15 μs coherence, 87% yield, scalable to 300 mm wafers; (Mayer et al., 7 May 2025)) and analog spiking neural hardware (BrainScaleS: ~10⁵ neurons, ~10⁸ synapses per wafer; DarwinWafer: 0.15 B neurons, 6.4 B synapses, 4.9 pJ/SOP, robust assembly via warpage-tolerant PCBlet/pogo techniques) (Zhu et al., 30 Aug 2025, Schmidt et al., 2023).

Photonic WSCs achieve wafer-scale squeezed-light sources with <0.2 dB variation and >3 dB direct quadrature squeezing, enabled by CMOS-compatible Si₃N₄ integration and advanced microresonator design, paving the way for scalable CV quantum processors, cluster states, and quantum-enhanced sensing arrays (Liu et al., 12 Sep 2025).

6. Network, Interconnect, and Scaling Topologies

Wafer-scale interconnects replace traditional switch-based direct topologies with distributed, switch-less mesh routers. Switch-Less Dragonfly-on-Wafers implements every Dragonfly “switch” as a mesh of chiplets/cores, eliminating external switches, slashing cost per port by >10×, and doubling local throughput (3 flits/cycle/chip vs. 1 in classic Dragonfly) (Feng et al., 14 Jul 2024). Bisection bandwidth for mesh architecture is given by $B_\text{bisec} = \sqrt{N} \cdot B$, with typical per-link bandwidth >800 GB/s. Virtual channel count for deadlock-free minimal routing is minimized; SL-DF logic demands only one extra VC above the baseline. Design principles generalize to topology hybrids and photonic links (Feng et al., 14 Jul 2024).

Physical integration on silicon interposers leverages high-density microbumps (signal to periphery, power to center), multi-level redistribution, and warpage-tolerant multi-step assembly (flip-chip → PCBlet → pogo-pin mainboard) to realize robust operational and thermal profiles at wafer scale (e.g., 34–36°C @ 100 W total power across DarwinWafer) (Zhu et al., 30 Aug 2025).

7. Design Guidelines, Challenges, and Perspectives

Architectural co-design for WSCs requires balancing compute, memory, and D2D/fabric bandwidth under strict area constraints ($A_w = a_C C + a_M M + a_B B_{D2D} = A_{\max}$). Optimal performance is achieved with moderate per-die DRAM (64–70 GB), high D2D bandwidth (>4 TB/s), square die and wafer arrays, location-aware memory placement, and enhanced per-core SRAM (≥1 MB) (Wang et al., 13 Dec 2025). Multi-fidelity DSE frameworks (Theseus) recommend core sizes in the 0.5–1 TFLOPS range, 50–60% area utilization per reticle, stacking DRAM bandwidth in 0.25–4 TB/s/100 mm²—with redundancy and failure models explicit in yield estimation (Zhu et al., 2 Jul 2024).

Key challenges include thermal management (densities 20–100 W/cm², requiring microfluidic or forced liquid cooling), fault tolerance across vast area-scale, and integrated, cross-layer optimization from circuit-to-app. Programmability and compiler toolchains must escape GPU-centered assumptions, providing explicit partitioning, mapping, and routing, as well as runtime remapping, calibration, and dynamic fault isolation (Hu et al., 2023, Essendelft et al., 18 Jun 2025).

Emerging directions include 3D stacking, heterogeneous integration (photonics, III–Vs, oxides), optical inter-wafer links for scaling, advanced micro-bump/power mesh planning, runtime reinforcement learning for placement, and expansion into new application domains (real-time physical simulation, quantum error correction, analog/hybrid computing). With sustained advances in packaging, interconnect, and co-design, WSCs are positioned to deliver orders-of-magnitude improvements in utilization, energy, and scalability, unlocking new paradigms across AI, quantum, neuromorphic, and photonic computing (Hu et al., 2023).