Thermal-Aware Via Farm Placement

• The paper demonstrates that optimizing TSV via farm placement and aspect ratio significantly reduces lateral heat blockage in thinned silicon while maintaining interconnect quality.
• It employs a thermal RC abstraction and simulated annealing methodology to balance thermal efficiency against constraints like area and wirelength in 3-D IC designs.
• The integrated electro-thermal co-design approach also mitigates electrical issues such as crosstalk and insertion loss, achieving multi-objective optimization in floorplanning.

Searching arXiv for the cited papers and closely related work on thermal-aware via farm placement. arXiv search query: (Chen et al., 19 Jul 2025) thermal-aware via farm placement TSV floorplanning thermal blockage HotSpot

Thermal-aware via farm placement is a 3-D IC physical-design methodology that treats dense through-silicon-via (TSV) farms as thermally active floorplanning objects rather than as purely electrical interconnects. In this formulation, a via farm is a cluster of TSV vias used for signal bus connections between layers, and its placement, shape, and aspect ratio are optimized to reduce lateral heat blockage in thinned silicon while preserving interlayer connectivity, area, and wirelength quality. The central observation is that TSVs can improve vertical heat conduction yet simultaneously degrade lateral heat spreading when organized into dense farms with small pitch and low metal-to-insulator ratio; this effect becomes especially important when silicon is thinned to roughly $10\text{–}100\,\mu m$ and local hotspots depend strongly on in-plane heat flow (Chen et al., 19 Jul 2025). A related line of work extends the same topic into electro-thermal co-design, showing that via placement also changes shielding, return paths, crosstalk, insertion loss, and effective anisotropic thermal conductivity, so placement cannot be optimized purely thermally or purely electrically (Gharib et al., 31 Mar 2026).

1. Thermal mechanism and design problem

The design problem arises from a mismatch between the conventional intuition about TSVs and the behavior of dense signal-bus via farms in modern 3-D stacks. Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. The thermal-aware placement literature distinguishes this vertical benefit from a separate lateral blockage effect that becomes increasingly important as TSV size and pitch continue to scale in the $\mu m$ range and the metal-to-insulator ratio becomes smaller. In dense farms, the effective thermal conductivity in the lateral $x/y$ directions is reduced relative to surrounding silicon, so the farm can interrupt lateral heat-dissipation paths and exacerbate local hotspots (Chen et al., 19 Jul 2025).

This effect is coupled to wafer thinning. Because 3-D IC wafers are aggressively thinned to roughly $10\text{–}100\,\mu m$, the silicon available to spread heat laterally is already limited. A dense TSV farm inserted into such a layer does not merely occupy routing real estate; it modifies the heat-flow topology of the substrate. The reported effect is not confined to the layers electrically connected by the farm. A via cluster can alter the thermal profile of layers it merely passes through, which makes via farm planning a stack-level rather than a single-layer problem (Chen et al., 19 Jul 2025).

A second dimension of the design problem is that these farms are signal-bus TSV clusters, not arbitrary thermal structures. Their placement must continue to satisfy interconnect connectivity between layers. Thermal-aware placement therefore operates under explicit physical-design constraints, balancing thermal improvement against wirelength, floorplan area, and aspect-ratio targets rather than pursuing temperature reduction in isolation (Chen et al., 19 Jul 2025).

2. Thermal RC abstraction and optimization objective

The thermal model is built on a thermal RC representation of via-farm regions. The key modeling move is to assign each via farm independent lateral and vertical thermal resistance components. At block level, a via-farm region is represented with $R_L$ for lateral heat flow and $R_v$ for vertical heat flow. The model is then extended to a grid suitable for HotSpot-based temperature estimation, with mixed cells combining silicon and via-farm material through effective resistances (Chen et al., 19 Jul 2025).

The physical motivation is expressed through the standard thermal resistance and heat-flow relations:

$R = \frac{h}{k \cdot A} \tag{1}$

and

$$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$

These relations motivate why thinning silicon and introducing low-conductivity composite via structures worsens lateral transport. The placement flow therefore introduces a heat-conduction efficiency metric

$$f_{HAB} = \frac{\Delta Q}{\Delta T \cdot \Delta t} = k \cdot \frac{A}{x}, \tag{6}$$

aggregated as

$f_H = \Sigma f_{HAB}. \tag{8}$

The floorplanning objective is explicitly formulated as

$\mu m$0

where $\mu m$1 is the final floorplan area, $\mu m$2 is the total heat-gradient efficiency, $\mu m$3 is a floorplan aspect-ratio regularizer, and $\mu m$4 is total wirelength (Chen et al., 19 Jul 2025).

In this formulation, thermal optimization is localized to the most consequential heat-flow regions. The algorithm seeks to maximize thermal conduction efficiency where the thermal gradient is highest, but it imposes strong penalties on area and wirelength so that thermal improvement does not come at the expense of physical-design quality. This suggests a “minimum-change” floorplanning regime in which via farms are adjusted just enough to remove blockages from important thermal paths while preserving the main structure of the electrical design (Chen et al., 19 Jul 2025).

3. Placement flow and geometric degrees of freedom

The proposed placement strategy is a two-level iterative optimization flow. First, the design is thermally analyzed layer by layer to identify hotspots and interlayer connectivity. Then, for each layer, the optimizer examines TSV-farm structures that traverse the layer and treats them as movable and reshappable soft blocks. Candidate aspect ratios are precharacterized so that a new geometry can be selected to minimize the thermal resistance in the flow direction. After that, the tool performs simulated-annealing-based placement using a deliberately local move set (Chen et al., 19 Jul 2025).

Each simulated annealing step executes one of two operations: it changes the aspect ratio of a TSV farm and recomputes its width and height, or it moves the farm to a new position in the floorplan. Downhill moves are accepted directly, while uphill moves are accepted probabilistically using the standard $\mu m$5 rule until cooling reaches a threshold $\mu m$6. The stated rationale is to avoid major macro disruptions while still escaping poor local placements. The outer loop iterates over layers, checks whether the stack-level average temperature has improved enough, and retains the design that achieves the largest overall temperature reduction (Chen et al., 19 Jul 2025).

This flow differs from a generic macro placer in two ways. First, the via farm is modeled as a thermal obstruction whose shape matters, not merely as a fixed interconnect terminal. Second, the method explicitly exploits anisotropy: a farm can be reshaped so that thermal resistance is reduced along the dominant heat-flow direction. A plausible implication is that aspect-ratio tuning is most useful when the local temperature field has a clear directional gradient, whereas pure relocation is more useful when the dominant problem is obstruction of a specific hotspot-to-sink path.

4. Experimental behavior in benchmark 3-D ICs

The experimental evaluation uses MCNC benchmark circuits including ami33, ami49, alpha, hp, and xerox, under both unit-level partitioning and core-level partitioning. The thermal analysis infrastructure combines the HotSpot compact thermal model with package and air cooling and via-farm-aware RC models. Reported technology parameters include TSV-farm thermal conductivity varied over $\mu m$7, TSV size and pitch about $\mu m$8, average core area $\mu m$9, power density $x/y$0, silicon thickness $x/y$1, and ambient temperature $x/y$2 (Chen et al., 19 Jul 2025).

For the MCNC unit-level cases, the reported average improvement across benchmarks is about $x/y$3 reduction in average chip temperature and $x/y$4 reduction in peak temperature, with negligible wirelength overhead and slight area reduction due to reshaping or replacement of TSV farms. The average over all listed benchmarks changes from $x/y$5 average, $x/y$6 peak, and $x/y$7 hottest block to $x/y$8, $x/y$9, and $10\text{–}100\,\mu m$0, respectively. Wirelength increases only marginally, around $10\text{–}100\,\mu m$1 on average (Chen et al., 19 Jul 2025).

Individual examples illustrate the scale of the effect. In ami33, the reported values change from $10\text{–}100\,\mu m$2 average and $10\text{–}100\,\mu m$3 peak to $10\text{–}100\,\mu m$4 average and $10\text{–}100\,\mu m$5 peak. In alpha, they change from $10\text{–}100\,\mu m$6 average and $10\text{–}100\,\mu m$7 peak to $10\text{–}100\,\mu m$8 average and $10\text{–}100\,\mu m$9 peak. In hp, the peak temperature changes from $R_L$0 to $R_L$1. The paper attributes these gains to moving farms away from the hottest lateral paths and reshaping them into more thermally favorable geometries while keeping interconnect topology disturbances small (Chen et al., 19 Jul 2025).

The multicore case study emphasizes stack-level redistribution rather than single-layer monotonic improvement. In a two-layer multicore example, whole-stack average temperature drops from $R_L$2 to $R_L$3. The bottom layer falls from $R_L$4 to $R_L$5, while the top layer changes from $R_L$6 to $R_L$7. The peak temperature of the bottom-layer hotspot decreases from $R_L$8 to $R_L$9, a reduction of $R_v$0. The description of CORE2 and CORE5 indicates that local BUS structures and the shared BUS0 benefit when repositioned away from the main heat-flow path. In a multicore-plus-memory stacking case, the reported reduction is $R_v$1 in core-layer peak temperature for the four-layer memory stack scenario, with about $R_v$2 steady reduction as the number of stacked memory layers increases (Chen et al., 19 Jul 2025).

5. Electro-thermal co-design of TSV networks

A broader treatment of thermal-aware via farm placement models the TSV array as a coupled electro-thermal network rather than as a purely thermal obstruction. In that setting, placement changes reflection coefficient $R_v$3, insertion loss $R_v$4, NEXT/FEXT crosstalk, shielding, current return paths, inductive and capacitive coupling, effective thermal conductivity of the substrate, lateral heat spreading, vertical heat removal, and local hot spots due to Joule heating. The practical conclusion is that optimizing only crosstalk or only thermal conductivity can miss the best overall layout (Gharib et al., 31 Mar 2026).

The analytical framework in this work extends a prior cylindrical interconnect model to multi-ground TSV arrays and combines a distributed RLCG equivalent circuit with a homogenized anisotropic thermal-conduction model. It computes broadband S-parameters and effective anisotropic thermal conductivities for arrays up to $R_v$5, achieving $R_v$6 relative Frobenius error across those array sizes. The corresponding physics-informed GNN surrogate, TSV-PhGNN, is pretrained on $R_v$7 analytical samples and fine-tuned with $R_v$8 HFSS samples, then generalizes to larger arrays with relative Frobenius error below $R_v$9 and nearly constant variance. The surrogate makes millisecond-scale inference possible, enabling exploration of millions of TSV configurations within minutes and reducing per-design evaluation time by more than six orders of magnitude (Gharib et al., 31 Mar 2026).

The optimization framework supports both signal/ground placement optimization and geometric parameter optimization over TSV radius, pitch, height, and oxide thickness. For the benchmark $R = \frac{h}{k \cdot A} \tag{1}$0 grid with 12 signal TSVs, the design space is

$R = \frac{h}{k \cdot A} \tag{1}$1

The search is accelerated by exploiting square-grid symmetry $R = \frac{h}{k \cdot A} \tag{1}$2, reducing the search space by up to $R = \frac{h}{k \cdot A} \tag{1}$3. The multi-objective Pareto formulation targets $R = \frac{h}{k \cdot A} \tag{1}$4, $R = \frac{h}{k \cdot A} \tag{1}$5, worst-case NEXT/FEXT, and $R = \frac{h}{k \cdot A} \tag{1}$6, $R = \frac{h}{k \cdot A} \tag{1}$7, $R = \frac{h}{k \cdot A} \tag{1}$8, thereby exposing explicit tradeoffs among signal matching, loss, isolation, and thermal transport. Reported outcomes include worst-case crosstalk improvement from about $R = \frac{h}{k \cdot A} \tag{1}$9 to about $$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$0 for the $$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$1, 12-signal benchmark, and to about $$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$2 for a relaxed 9-signal case. Among Pareto-optimal designs, the best crosstalk design achieves worst Xtalk $$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$3 with $$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$4, while the best thermal design reaches $$H_{AB} = \frac{\Delta Q}{\Delta t} = k \cdot A \cdot \frac{\Delta T}{x}. \tag{5}$$5 (Gharib et al., 31 Mar 2026).

This electro-thermal perspective does not replace floorplanning-level thermal blockage analysis; rather, it broadens it. The earlier floorplanning work focuses on the lateral blockage created by dense signal-bus farms in thinned silicon, whereas the later network-level framework makes explicit that those same farms are also electromagnetic structures whose signal/ground assignment and sparsity determine both coupling and thermal transport. A plausible implication is that future thermal-aware via farm placement may increasingly require joint optimization across floorplanning, signal integrity, and package-level thermal reliability.

6. Scope, misconceptions, and unresolved boundaries

A recurrent misconception is that TSVs are uniformly beneficial for heat removal because they improve vertical conductivity. The thermal-aware placement literature qualifies this claim: a dense signal-bus via farm can increase vertical conduction while simultaneously reducing lateral conduction through a thinned layer. When the dominant thermal bottleneck is in-plane spreading rather than through-thickness extraction, the net effect can be a hotter local region rather than a cooler one (Chen et al., 19 Jul 2025).

A second misconception is that via farm placement can be treated as an electrical optimization followed by an independent thermal check. The electro-thermal framework argues that changing placement changes both the EM coupling environment and the substrate’s effective heat-flow paths. Dense metallic vias can improve heat conduction yet worsen electrical coupling if poorly arranged; conversely, spacing vias or reassigning them as ground can suppress crosstalk but may reduce thermal conduction. This establishes via farm placement as a multi-physics co-design problem rather than a single-objective layout exercise (Gharib et al., 31 Mar 2026).

The principal stated limitation of the floorplanning method is that it does not explicitly optimize timing or power and assumes that thermal-aware modifications are small enough not to cause significant degradation. It also focuses mainly on floorplanning-level placement, leaving very fine-grained microarchitectural timing effects and broader routing interactions outside the scope. The surrogate-based electro-thermal framework addresses a different scale of the problem—dense array layout and geometry exploration with full-wave and thermal sign-off validation—so the two approaches are complementary rather than interchangeable. This suggests that thermal-aware via farm placement remains an open integration problem across abstraction levels, from floorplan soft-macro manipulation to array-level Pareto optimization and final sign-off (Chen et al., 19 Jul 2025).