ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators

Abstract: Chiplet-based DNN accelerators provide a scalable path to balance performance and yield for modern AI workloads. However, such systems face critical challenges in area and thermal constraints. Design space optimization should jointly consider fine-grained task modeling, chiplet granularity, core granularity, and critical physical constraints. To the best of our knowledge, this is the first framework that involves all these factors. In this work, we propose ThermoDSE, a thermal-aware and comprehensive design space exploration framework for chiplet-based DNN accelerators. ThermoDSE integrates existing fine-grained modeling techniques into a unified simulation and optimization framework that jointly considers architecture design, task orchestration, and inter-chiplet communication under strict thermal and area constraints. Experimental results show that ThermoDSE achieves up to 3.5x improvement in Energy-Delay-Inverse-Yield, defined as E times D times inverse Y, compared with state-of-the-art Simba and other baselines. Furthermore, relative to simulated annealing and reinforcement learning-based methods, ThermoDSE converges to better design points with 3.7x and 29.4x runtime speedups, respectively.

• The paper presents a comprehensive thermal-aware design space exploration framework for chiplet-based DNN accelerators that couples fine-grained architectural modeling with realistic thermal simulation.
• It introduces a scalable method using transductive experimental design and constrained Bayesian optimization to reduce the energy-delay-yield product by up to 3.5× and accelerate iteration speeds by up to 29.4×.
• The work highlights the critical role of thermal and area constraints in chiplet granularity and task orchestration, ensuring robust and physically realizable accelerator designs.

ThermoDSE: A Thermal-Aware and Comprehensive DSE Framework for Chiplet-Based DNN Accelerators

Introduction and Context

As scaling constraints and thermal challenges limit monolithic system-on-chip (SoC) scaling, chiplet-based architectures have become the de facto solution for constructing high-throughput Deep Neural Network (DNN) accelerators. However, these multi-chiplet DNN systems introduce new design complexities, particularly concerning area, communication, and thermal constraints that must be jointly optimized with architectural parameters. Previous methods—ranging from coarse-grained design space exploration (DSE) to reinforcement learning-based approaches—are typically limited either in modeling fidelity or in search efficiency, often neglecting crucial interactions between architectural granularity, physical constraints, and chiplet yield.

The ThermoDSE framework addresses these deficiencies by providing a physically-realistic, thermal-aware, and efficiency-optimized DSE environment for chiplet-based DNN accelerators. Notably, the framework integrates fine-grained task orchestration, jointly modeling chiplet/core granularity, inter-chiplet spacing (ICS), buffer architecture, and interconnect bandwidth, all under stringent area and thermal constraints. Moreover, ThermoDSE introduces a scalable, constraint-aware Bayesian optimization strategy, leveraging transductive experimental design (TED) for initialization and scalable constrained Bayesian optimization (SCBO) for iterative search.

Framework Overview

ThermoDSE's architecture models a physically realizable multi-chiplet DNN accelerator. Each core is a highly parameterized NPU with both matrix and vector units, equipped with a sophisticated memory hierarchy enabling fine-grained, $\mu$task-parallel execution. Chiplets are organized over a shared interposer, and both intra-chiplet (NoC) and inter-chiplet (NoP) communication are explicitly, accurately modeled.

Figure 1: (a) Chiplet-based DNN accelerator diagram, (b) Detailed architecture of a single NPU core.

A significant advancement in ThermoDSE is its integration of detailed thermal simulation via HotSpot, using power maps derived from cycle-accurate architectural simulation. This enables fidelity in reporting both steady-state and peak temperatures associated with diverse workload mixes and resource allocations.

Figure 3: Cross-sectional schematic of the chiplet-based accelerator, illustrating compute die, NoC, micro-bumps, and interposer interconnects.

Fine-Grained Task Orchestration and Thermal Implications

ThermoDSE employs a fine-grained, graph-based task orchestration engine: neural network layers are partitioned into $\mu$tasks, which are then scheduled and mapped onto the physical NPU array. The mapping strategy is both utilization- and thermal-aware, preferring to assign high-power tasks to physically peripheral cores to alleviate thermal hotspots—an explicit response to lateral heat accumulation.

Figure 5: Example of $\mu$task scheduling and mapping for ResNet block structure onto a $2\times2$ core tiled accelerator.

Thermal heterogeneity across workloads is substantial, given the significantly varying spatial and temporal power footprints across modern DNNs (e.g., BERT, AR/VR, GoogLeNet). The coupled impact of workload mix, resource allocation, and physical placement is visible in per-chiplet and global thermal maps.

Figure 6: Thermal distribution for three representative workloads (GoogLeNet, Transformer/BERT, AR/VR), highlighting distinct temperature peaks and spatial patterns.

Multivariate Performance Objective and Constraint Handling

The design-space cost function is EDYP: $EDYP = E \times D \times Y^{-1}$, where energy, delay, and inverse die yield are balanced. The optimizer aims for EDYP minimization under two explicit constraints: maximum peak temperature and total interposer area.

ThermoDSE’s performance model hierarchically integrates latency, DRAM/NOC/NOP access, on-chip buffer utilization, and compute array alignment (including edge/zero-padding inefficiencies in systolic array mappings). The energy model aggregates DRAM, computation, buffer hierarchy, NoC, and NoP contributions with realistic switching activity and communication assumptions. Yield follows a negative binomial model, crucial in high-chiplet-count configurations.

TED + SCBO: Efficient Constrained DSE in Large Spaces

Given the billion-point design space, ThermoDSE uses active-learning-based TED to construct an initial, maximally-informative sample set, ensuring surrogate GP models are well-aligned with the true response surface. Subsequently, SCBO iteratively updates trust-region-based GPs for both objectives and constraints, focusing candidate search in the feasible boundary region—where optimal solutions generally lie.

Figure 4: High-level flow of the ThermoDSE design space exploration framework, showing integrated architectural modeling, thermal evaluation, and constraint-aware Bayesian optimization.

The practical effect is that ThermoDSE converges on physically sound, low-EDYP solutions $3.7\times$ to $29.4\times$ faster (in terms of iterations until best design) than SA (TESA-style) and RL-based (Chiplet-Gym) optimizers.

Figure 2: Convergence characteristics for various SCBO trust-region thresholds, demonstrating rapid cost minimization and efficient feasible set exploration.

Experimental Results and Analysis

Design Efficacy and Validity

ThermoDSE not only identifies designs surpassing those of Simba, TESA, and Chiplet-Gym in both energy-delay product and temperature compliance but also demonstrates the inadequacy of analytical or coarse DSE: e.g., Chiplet-Gym underestimates peak temperature by $9.8^\circ$C and yields up to 53% error in energy prediction. The optimal ThermoDSE-derived design is a 2-chiplet, $5\times4$-NPU system with elevated ICS and a large, well-utilized matrix unit; this configuration substantially beats both serial and parallel, buffer-bounded baselines in the combined EDYP metric.

Figure 8: Normalized energy and delay for various configurations and models (relative to Simba baseline).

Figure 9: Pareto front of EDYP cost versus peak temperature under fixed area/thermal constraint; designs produced by ThermoDSE lie tightly on the constraint boundary.

Domain-Specific Insights

ThermoDSE exposes thermal bottlenecks and communication/compute trade-offs as a function of both chiplet granularity and mapping. For compute-bound DNNs, maximizing core utilization with sufficient on-chip reuse is critical; for comm/data-bound workloads (e.g., BERT), the mapping of attention heads and data fusion steps drive both delay and energy.

Resource allocation analysis reveals that >49% of area is optimally assigned to compute units, with on-chip buffers taking a subordinate 14%. Importantly, cooling infrastructure (TIM, spreader, sink) is also non-negligible in area accounting.

Figure 7: Area breakdown and thermal map of optimal ThermoDSE design under $300\,mm^2$ and $\mu$0C constraints.

Sensitivity to Area and Thermal Envelope

Reducing area constraints (e.g., to $\mu$1) imposes a sharper trade-off, restricting thermal headroom and feasible mappings; minimum feasible EDYP grows substantially. The optimizer adaptively shifts designs to fewer, larger chiplets with lower interconnect cost.

Figure 10: EDYP cost versus peak temperature under a more stringent $\mu$2 area ceiling; a tight coupling of area and thermal feasibility is evident.

Implications and Future Directions

ThermoDSE provides clear evidence that:

• Chiplet granularity is a first-order design knob: Aggressive partitioning incurs inter-chiplet energy/thermal overheads that cannot be ignored at realistic scales. Early, integrated exploration is crucial.
• Fine-grained orchestration is mandatory: Accurate performance/thermal modeling requires realistic task mapping, buffer, and communication dynamics; analytical shortcuts are insufficient and often fundamentally misleading.
• SCBO-based constraint-aware exploration is tractable at scale: Trust region adaptation and surrogate fidelity drastically reduce both iteration cost and search redundancy.

Practically, ThermoDSE’s methodology is generalizable to other multi-die or advanced (3D-stacked) heterogeneous DNN accelerators; future extensions towards true 3D stacking would need to consider additional vertical thermal bottlenecks, die-die reliability, and possibly more sophisticated multi-fidelity surrogate models for early-/late-stage optimization.

Conclusion

ThermoDSE establishes a new technical baseline for holistic, thermal-aware DSE of chiplet-based DNN accelerators. Integrating fine-grained architectural and physical modeling with efficient, constraint-aware Bayesian optimization, it substantially outperforms prior art in both result quality (up to $\mu$3 EDYP improvement vs Simba baseline) and search efficiency ($\mu$4 speedup vs RL-based DSE). Its practicality in discovering chiplet/core/buffer/interconnect configurations robust to real-world area and thermal constraints directly informs next-generation scalable AI system design.

The principles and capabilities demonstrated by ThermoDSE will inform both the physical design automation community and DNN accelerator architects as chiplet-based and 3D-stacked solutions become industry-standard.