TDM Voltage Control: Cryogenic & Trapped-ion
- TDM-based voltage control systems are hardware architectures that use time-division multiplexing to bias, route, and read multiple voltage channels with precise timing and feedback.
- These systems recycle high-value analog resources via synchronized switching and sample-and-hold circuits, optimizing settling time and reducing crosstalk in challenging environments.
- Implementations in Athena X-IFU and trapped-ion processors demonstrate effective performance with metrics like 2.80 eV resolution and 37.5 kHz refresh rates, highlighting scalable design potential.
A TDM-based voltage control system, as the term is represented in the cited literature, is a hardware or mixed-signal architecture in which time-division multiplexing is used to bias, route, preserve, or read out multiple voltage-defined channels through shared resources. Two experimentally developed realizations appear most directly. One is the cryogenic TES/SQUID readout chain being integrated for the Athena X-IFU focal-plane assembly, where the TES are continuously dc-biased and the readout is multiplexed by row addressing, SQUID switching, and digital flux-locked-loop feedback. The other is a cryogenic demultiplexed trap-electrode controller for scalable trapped-ion quantum processors, where a room-temperature DAC serializes electrode voltages and cryogenic sample-and-hold hardware reconstructs per-electrode outputs near the trap (Vaccaro et al., 2024, Ohira et al., 18 May 2026).
1. Definition and scope
In the cryogenic instrumentation literature, TDM is not merely a communications convenience. It is part of the electrical plant. The multiplexing pattern determines settling, aliasing, crosstalk, bandwidth, and the practical meaning of voltage bias. In the Athena X-IFU test-bed, the signal chain couples continuously dc-biased TES detectors to first-stage SQUIDs, switches rows sequentially, amplifies the selected signal through a series SQUID array, digitizes at room temperature, and closes the SQ1 flux-locked loop digitally. In the trapped-ion case, TDM is implemented as demultiplexed sample-and-hold voltage delivery: one DAC stream is routed to many electrodes by synchronized cryogenic switches and holding capacitors (Vaccaro et al., 2024, Ohira et al., 18 May 2026).
A useful boundary of the term is provided by adjacent literatures that explicitly state they are not TDM. Several HVDC and power-distribution papers analyze slack-bus, droop, DAPI, deadband PI, distributed feedback, model-less robust control, digital twins, or limited-communication voltage regulation, but they also state that they do not explicitly discuss time-division multiplexing, packet scheduling, or sampled-data TDM implementation (Andreasson et al., 2016, Andreasson et al., 2015, Magnusson et al., 2017). In that sense, TDM-based voltage control is a narrower category than “voltage control system” in general.
2. Shared architectural pattern
Despite their different physical domains, the direct TDM systems in the cited work share a common structure: a smaller number of high-value analog resources are reused in time, while local state retention or dynamic feedback preserves channel-specific behavior between visits.
| System | Shared TDM resource | Reported operating result |
|---|---|---|
| Athena X-IFU TES/SQUID test-bed | Row-addressed SQ1/SSA readout of continuously dc-biased TESs over a long flex harness | eV at 5.9 keV with 16-row multiplexing |
| Trapped-ion QCCD static electrodes | Cryogenic demultiplexed sample-and-hold voltage delivery | 32 channels at approximately 27 K, 37.5 kHz effective update rate, |
| Trapped-ion QCCD dynamic electrodes | Four-channel cryogenic demultiplexed waveform delivery | 4 channels at approximately 14 K, 1 MHz effective update rate, comparable output range |
The CMB-S4 readout model gives the same architectural logic in a more abstract form. It describes a TDM system for DC-voltage-biased TES bolometers in which all detectors in a column share a common voltage bias, each detector is coupled to an SQ1, one row is enabled at a time using Row Select and Chip Select signals, and the required multiplexing factor is 80. The model is then used to predict bandwidth and noise performance of the full circuitry and interconnections, rather than only individual components (Goldfinger et al., 2023).
This suggests that, in TDM voltage systems, the decisive design variable is not only nominal bias magnitude. It is the joint configuration of switching sequence, analog bandwidth, local hold behavior, interconnect parasitics, and the timing of when a channel is considered valid.
3. Cryogenic TES/SQUID implementation for Athena X-IFU
SRON, with hardware from NASA Goddard Space Flight Center and NIST, developed a cryogenic TDM test-bed as a pathfinder for Athena X-IFU’s Focal Plane Assembly Demonstration Model. The architecture comprises a 50 mK detector stage, a 4 K SQUID amplifier stage, a long warm-to-cold flex harness, warm front-end analog electronics, and digital timing and feedback electronics. At 50 mK, the “snout” hosts both the TES detector array and the TDM MUX chips. The TES array used here is a kilo-pixel array with TES dimensions $75\times 75~\upmu\mathrm{m}$, normal resistance , and transition temperature ; the average single-pixel energy resolution is quoted as 2.3 eV at 6 keV. The MUX chips contain the first-stage SQUIDs, the shunt resistor used to voltage-bias the TES, and Nyquist inductors with and $R_{sh}=69~\upmu\Omega$. The 50 mK stage is stabilized at 50 mK to about $1~\upmu\mathrm{K}$ using a ruthenium oxide thermometer and a heater (Vaccaro et al., 2024).
The voltage-control content is explicit even though the paper is framed as a readout-integration study. The TES are “continuously dc-biased,” and the shunt resistor on the MUX chip provides the low-impedance voltage bias. The warm analog front end, the NIST “Tower,” sets the quiescence operating point of detectors, SQ1s, and the SSA. Digital control is provided by the NASA GSFC Digital Readout Electronics, composed of a Column Box and a Row Box. Using clocks derived from a 245.76 MHz master clock, the DRE generates row-addressing signals, switches rows through flux-actuated switches, provides digital feedback for the SQ1 flux-locked loop, and handles acquisition and streaming. In TDM terms, each SQ1 is one row; all rows form one frame; columns are read out in parallel, although only one usable column was available in the installed DRE. The intended X-IFU architecture is $48$-row 0 1-column TDM with 160 ns row time (Vaccaro et al., 2024).
The central systems issue was the long flex harness between the 4 K board and the warm Tower electronics. It consists of 10 flexes, each with 8 Cu single-ended signal lines, with total length 1.54 m, compared with the legacy harness length of about 43 cm and the future X-IFU requirement of 2.3 m. The redesign kept electrical resistance below 2 and maintained signal-return capacitance near legacy values, but increased inductance. That increased electrical crosstalk and caused underdamped ringing at 8–9 MHz. With short legacy flexes, the same system had delivered 2.8 eV at 6 keV in 32-row readout. With the long flexes, 32-row operation at the nominal 160 ns row time did not permit stable FLL operation at all; 24-row operation was stable but only about 7 eV; reducing to 16 rows and expanding row time to about 360–366 ns restored 2.8 eV performance (Vaccaro et al., 2024).
The paper also reports system-level debugging measures that are directly relevant to voltage-control engineering. A “star” grounding scheme used the top of the cryostat as the single reference; all electronics were grounded to this reference using thick copper braids; the Column and Row Boxes were powered through an isolation transformer; optical fibers decoupled the Tower and Column Box from the measurement computer. Even after that, strong 50 Hz and harmonic lines appeared because of EMI coupling in an approximately 3 m loop formed by HDMI and BNC cables between the DRE and Tower. Bundling and intertwining those cables reduced loop area, and wrapping the bundle in aluminum foil completely removed the 50 Hz lines. Magnetic sensitivity was also tuned, yielding an optimal local canceling field of about 150 nT with no evident gradient across the array (Vaccaro et al., 2024).
A useful low-level validation came from the superconducting TES state. The measured SQUID noise showed Johnson noise from the shunt resistor and the roll-off associated with the “Johnson noise cutoff 3,” and the measured values “correspond very well to the expected values,” which the authors interpret as verification of the cold readout circuit and thermometry. This establishes that, in a TDM voltage-biased cryogenic chain, passive bias and filtering elements can be verified from their spectral signatures even before full multiplexed X-ray operation (Vaccaro et al., 2024).
4. Timing, settling, bandwidth, and aliasing
The Athena test-bed shows that TDM voltage behavior is dominated by transient timing rather than only by static bias accuracy. In the short-harness architecture, 160 ns row time left enough settling margin for 32-row operation. With the 1.54 m harness, 160 ns was too short for the ringing to decay before the ADC integration window. NIST’s long-flex tests used a 360 ns row time with 224 ns settling and 136 ns sampling, deliberately integrating over one oscillation period to average out the ringing. At SRON, the GSFC DRE allowed at most 16 integration samples, so the maximum sampling time was 4. With the same row time and settling time but only 65 ns sampling, summed performance was 3.1 eV at 5.9 keV. The fix was to use the additional 5 ns by increasing settling time and shifting the 65 ns integration window as far as possible from the transient, up to right before the falling edge of the square wave smoothed by the 4th-order low-pass filter. After this retuning, the system recovered 6 eV at 5.9 keV with 16-row multiplexing (Vaccaro et al., 2024).
The CMB-S4 end-to-end model generalizes the same constraint in more abstract terms. It describes a TDM readout for DC-voltage-biased TES bolometers in which a voltage bias is applied simultaneously to the detectors of an entire column, and row selection is performed by RS and CS signals. The model emphasizes that the bandwidths of the SSA and SQ1 need to extend out to the row rate so that the time for all switched inputs to settle at their new values is less than the dwell time spent waiting before recording a measurement and moving on to the following row. It also emphasizes that because the analog bandwidth is larger than the multiplexed sampling rate, high-frequency noise aliases into the sampled band. To predict this correctly, broadband noise is simulated, filtered by the end-to-end circuitry and wiring, then resampled at the multiplexed rate. The required multiplexing factor for CMB-S4 is 80; the paper cites practical comparison points of 64 rows at 500 kHz in AdvACT, 41 rows at 770 kHz in BICEP Array, and 32 rows at 6.25 MHz in X-ray systems (Goldfinger et al., 2023).
The same model identifies dominant noise sources that matter in any switched voltage-biased chain: warm room-temperature amplifier noise, Johnson noise of the SQ1 shunt resistor, Johnson noise of the TES shunt resistor, and Johnson noise of the manganin cryocable connecting the 4 K SSA to 300 K electronics. It also attributes disagreement between modeled and measured spectra in the 100 kHz–1 MHz range to environmental pickup, likely common-mode pickup in the SQ1 loop circuit. This reinforces the broader lesson from the Athena integration effort: a TDM voltage system is constrained by co-designed biasing, switching, wiring, and warm-electronics noise, not by any one block in isolation (Goldfinger et al., 2023).
5. Cryogenic demultiplexed electrode control for trapped-ion QCCD processors
The trapped-ion realization addresses a different bottleneck: vacuum feedthrough count in QCCD architectures, which require on the order of ten trap electrodes per qubit. The paper distinguishes two electrode classes. Static electrodes are used for trap-potential compensation, fabrication-error correction, and environmental compensation; they need stable DC voltages over about 7 but not rapid updates. Dynamic electrodes are used for ion shuttling, splitting, merging, and rotation; they require arbitrary time-varying waveforms, also over approximately 8, with per-electrode update rates on the order of MHz. The TDM solution is a cryogenic demultiplexed sample-and-hold system: if 9 electrodes must each be refreshed at rate $75\times 75~\upmu\mathrm{m}$0, then the DAC must output at total rate $75\times 75~\upmu\mathrm{m}$1, and the available charging window per slot is $75\times 75~\upmu\mathrm{m}$2 (Ohira et al., 18 May 2026).
For static electrodes, the implemented system used 32 channels at approximately 27 K. The room-temperature TDM signal-generation board comprised a Digilent Cmod A7 FPGA, an AD3542 DAC driven by SPI, an AD810 op-amp, and relay-switched output paths. The cryogenic DEMUX board used two stages of TMUX6208 switches arranged as 4 outputs in the first stage and 8 in the second stage, giving 32 channels total on a board of approximately $75\times 75~\upmu\mathrm{m}$3. The first-stage holding capacitor was $75\times 75~\upmu\mathrm{m}$4 and the second-stage capacitor $75\times 75~\upmu\mathrm{m}$5. Because TMUX6208 has an on-capacitance of about $75\times 75~\upmu\mathrm{m}$6, the system required a two-step charging sequence: charge the four first-stage capacitors sequentially, then activate the corresponding second-stage switch. A full refresh therefore required 40 DAC steps, so the effective refresh rate was $75\times 75~\upmu\mathrm{m}$7, rather than the nominal $75\times 75~\upmu\mathrm{m}$8 (Ohira et al., 18 May 2026).
This static system achieved an output range of $75\times 75~\upmu\mathrm{m}$9 per channel. The measured hold-droop rate for a held 0 output was 1, corresponding to an approximate drop of 2 over the 3 refresh interval at 37.5 kHz. The worst-case measured crosstalk was about 4. The implementation reduced feedthrough connections from 32 to 8—one analog line plus seven digital control lines—and reduced room-temperature DAC count from 32 to 1 (Ohira et al., 18 May 2026).
For dynamic electrodes, the implemented system used four channels at approximately 14 K. The room-temperature source used a Cmod A7 FPGA, an AD9707 DAC with 14-bit parallel input, and two cascaded output amplifiers, AD8099 and LM7171. The cryogenic DEMUX board used a TMUX6111 four-channel switch and 5 hold capacitors. With a 4 MHz DAC update rate and 4-way multiplexing, the effective per-channel update rate was 1 MHz, with comparable output range. The authors observed periodic output transients with period about 6, consistent with the 1 MHz update rate. Crosstalk from channel 1 into channels 2, 3, and 4 was measured as 7, 8, and 9, respectively. The source of the 0 transients was not fully resolved (Ohira et al., 18 May 2026).
The paper is careful about the scope of its claims. It demonstrates cryogenic electrical operation of both static and dynamic TDM voltage control, but not full trapped-ion operation in this cryogenic configuration. It also notes that TMUX6111 lacks an integrated digital decoder, so the four switches require four separate digital control signals, which is acceptable for a proof-of-concept but not yet optimal for large-scale dynamic-electrode control. A plausible implication is that future scalable versions will require more integrated cryogenic decoder logic.
6. Relation to adjacent voltage-control literatures and recurring misconceptions
A recurring misconception is to treat all “voltage control” papers as TDM papers. The adjacent literature is technically relevant but conceptually distinct. In MTDC networks, transient performance comparisons among slack-bus control, decentralized droop, and DAPI are explicitly continuous-time and not TDM; the same is true for decentralized deadband PI and distributed averaging controllers for HVDC, even when they use communication graphs or neighbor-to-neighbor exchange (Andreasson et al., 2016, Andreasson et al., 2015, Andreasson et al., 2014). In distribution networks, limited-communication Volt/VAR control with 2 bits per iteration, optimal distributed feedback voltage control under limited reactive power, model-free zeroth-order voltage control, model-less robust voltage control with RLS-estimated sensitivities, and experimental measurement-based robust control are all voltage-control systems, but they are not time-division multiplexed systems in the hardware sense addressed by the cryogenic papers (Magnusson et al., 2017, Qu et al., 2018, Gupta et al., 2023).
Another misconception is that longer interconnects mainly threaten TDM systems through DC resistance. The Athena test-bed shows the opposite emphasis: the 1.54 m harness was redesigned to keep resistance below 1 and capacitance near legacy levels, yet the decisive failure mode was increased inductance, which produced enhanced crosstalk, 8–9 MHz ringing, and settling constraints inside the required 2 MHz readout bandwidth. Likewise, the trapped-ion work shows that the decisive issues are not static voltage range alone but slot-time charging, hold-capacitor behavior, parasitic switch capacitance, droop, and switching artifacts (Vaccaro et al., 2024, Ohira et al., 18 May 2026).
A third misconception is to overstate demonstrated remedies. In the Athena system, the switch from single-ended to differential readout combined with active LNA input termination is expected to reduce ringing significantly, but the paper does not report measured before/after differential results. In the trapped-ion system, cryogenic TDM operation is demonstrated for static and dynamic electrode classes, but no integrated trapped-ion trapping or shuttling experiment is reported in that cryogenic configuration. In both cases, the results are system-enabling rather than exhaustive (Vaccaro et al., 2024, Ohira et al., 18 May 2026).
Taken together, the cited work supports a precise characterization of a TDM-based voltage control system: it is a switched electrical system in which voltage bias, sample timing, transient settling, interconnect parasitics, and local hold or feedback mechanisms are co-designed so that many channels can share limited wiring or readout resources without unacceptable degradation. In cryogenic sensor readout, that co-design restored nominal long-flex performance of 3 eV at 5.9 keV with 16-row multiplexing. In cryogenic trapped-ion control, it yielded 32 static channels at approximately 27 K with 37.5 kHz effective refresh and a four-channel dynamic system at approximately 14 K with 1 MHz effective refresh, establishing TDM as a practical route to feedthrough reduction for scalable hardware (Vaccaro et al., 2024, Ohira et al., 18 May 2026).