Control Line Multiplexing Scheme

Updated 9 November 2025

Control line multiplexing is a hardware–software strategy that shares one physical control line among multiple quantum, electronic, or photonic devices using spatial, frequency, or time-domain techniques.
It reduces wiring complexity and thermal loads while enabling scalable architectures in systems like superconducting qubits and mesoscopic transport channels.
Practical implementations integrate on-chip diplexers, cryogenic switches, and filters to maintain high fidelity and low crosstalk in multiplexed control applications.

A control line multiplexing scheme is a hardware or co-designed hardware–software architecture that enables a single physical control line (or a reduced number of lines relative to the number of devices) to address, actuate, and manage the state or parameters of multiple quantum, electronic, or photonic devices. Multiplexing, realized via spatial, frequency, or time-domain partitioning, is essential for scaling large arrays in regimes where per-device control lines would exceed chip, cryostat, or system-level interconnection limits. This article surveys canonical multiplexing architectures and analytical models for superconducting qubit arrays, photonics, mesoscopic transport, and optimal control on matrix Lie groups, emphasizing implementations, trade-offs, and measurable performance bounds.

1. Physical Principles and Multiplexing Modes

Control line multiplexing exploits resource sharing in the spatial, frequency, or temporal degree-of-freedom of device addressing and actuation:

Spatial multiplexing: Routing elements (switching FETs, gating trees, or binary-encoded multiplexer ICs) steer analog or digital control signals to one of many devices, typically via on-chip or board-level hierarchical networks (Al-Taie et al., 2013, Bian et al., 27 Mar 2024).
Frequency multiplexing: Devices (e.g., qubits or couplers) are arranged such that their control Hamiltonians respond selectively to excitation at distinct resonance frequencies, with on-chip bandpass or stopband filers enforcing spectral isolation (Shi et al., 2023).
Time multiplexing: A time-division protocol sequentially connects a single physical line to multiple devices by rapidly toggling switches or addressing decoders, with serialization/deserialization logic ensuring device-specific timing and synchronization (Gaetano et al., 21 Oct 2025, Richter et al., 28 Aug 2025, Bian et al., 27 Mar 2024).
Hybrid schemes may integrate two or more of the above to optimize wiring reduction and operational efficiency (e.g., shared frequency-multiplexed lines augmented by time-multiplexed switching) (Shi et al., 2023).

Multiplexing increases the “fanout” of each cryostat or chip connection, relaxing constraints on interposer, package, or cryogenic refrigerator I/O, but introduces new considerations for noise, crosstalk, signal integrity, and control signal scheduling.

2. Device-Level Implementations

Superconducting Qubits: Combined Microwave and Flux Lines ("XYZ Line")

The “XYZ line” architecture coalesces both the microwave (XY) and flux-bias (Z) drives for a superconducting transmon qubit onto a single on-chip control trace via a cryogenic diplexer (Manenti et al., 2021). The schematic consists of separate MW (3–7 GHz, ≈66 dB attenuation) and DC–1.5 GHz (Z, 20 dB attn) inputs feeding a lumped-element bandpass/low-pass splitter; the combined output is routed above each qubit with capacitive coupling for XY and a ground-referenced inductor for Z. Key optimization parameters include:

Mutual inductance $M \approx 500\,\mathrm{fH}$ (line-to-SQUID),
Capacitance $C_c$ (few $\mathrm{fF}$ ) between line and qubit pad,
Matched $50\,\Omega$ impedance for both XY and Z paths.

The table below summarizes the realized device metrics:

Parameter	Value/Range	Notes
Qubit coherence: $T_1$	Median 53 $\mu$ s (fluct. $\pm10$ )	Comparable to split-line devices
Hahn-echo $T_2^E$	$\approx49\,\mu$ s	At sweet-spot
MW→Flux cross-injection	$1.6\times10^{-4}\,\Phi_0$ per $\pi$ -pulse	Frequency shift $\|\delta f\| \ll$ linewidth
Randomized benchmarking	$>99.5\%$ ( $99.77\pm0.02\%$ on Q1)	100 ns DRAG pulse
Port count reduction	2 $\to$ 1 per tunable qubit	One XYZ line replaces separate XY + Z

This design reduces on-chip perimeter routing complexity and pin count but requires a custom diplexer per qubit and must manage MW insertion loss and total attenuation budgeting.

Quantum Transport: On-Chip Binary-Tree Multiplexer

In mesoscopic device arrays (e.g., split-gate transport channels), binary-tree multiplexers fabricated in a 2DEG deplete selected conduction paths by negatively biased Schottky gates (Al-Taie et al., 2013). A cascade of row- and column-selectors enables unique device addressing via $2^{N_{addr}/2}$ outputs per multiplexer with only $N_{addr}$ addressing gates and three global bias/measurement lines, scaling as $D = 2^{N_{select}/2} \times 2^{N_{columns}}$ per chip. Measured yields reach 94% fabrication, with quantum yields (appearance of 1D conductance plateaux at $2e^2/h$ ) as high as 86% post-illumination.

Time-Multiplexed Cryogenic and Photonic Control

In time-multiplexed electronic/photonic systems, current-mode or voltage-mode MUX/DEMUX ASICs on chip serialize/deserialize feedback and actuation signals (Gaetano et al., 21 Oct 2025). For example, a monolithically integrated 11:1 PD MUX and 1:14 heater DEMUX on a 4.3 mm × 3 mm die allows single-line read/write of 25 analog signals, with 0.6 mV S/H noise and negligible bandwidth penalty (25 Gb/s transmission, phase sensing accuracy π/250) and >2.5× pin-count reduction.

3. Multiplexing in Quantum Control and Scaling

Frequency-Multiplexed Quantum Gate Execution

Frequency-multiplexed schemes allow a single MW or flux-bias line to control $M$ qubits/couplers by engineering distinct transition frequencies and passband filters for each device (Shi et al., 2023). The total Hamiltonian is

$H_{drive}(t) = \sum_{j=1}^M \Omega_j(t)\,\sigma_x^j \cos(\omega_j t),$

with multi-tone pulses $V_{line}(t) = \sum_j V_j(t)\cos(\omega_j t)$ channeled through matched transmission lines and on-chip filters with stop-band attenuation $A \geq 40\,\mathrm{dB}$ . Gate fidelities surpass $99.9\%$ for $M \sim 100$ , with residual cross-talk errors controlled by calibration and filter design.

The technique requires careful software compilation to synchronize gate layers, e.g., mapping single-qubit layers to aligned π/2-pulse sequences (U3 decomposition), and employs co-designed calibration, virtual-Z tracking, and leakage monitoring. Simultaneous gate execution on shared lines is possible as pulse selectivity is guaranteed by the bandpass structure of on-chip filters.

Time-Multiplexed Quantum Control: Serialization Overhead

Time-domain multiplexing leverages cryo-CMOS switches or demultiplexers at the lowest temperature stage, where exactly one out of $k$ qubits is enabled at any given moment for gate operations (Richter et al., 28 Aug 2025). Overhead analysis shows that, unless the circuit is fully saturated with concurrent single-qubit gates, the execution time overhead grows only as $O(\ln k)$ :

$T_{overhead}(k) \approx p\,N_1^{routed} t_{1q} \ln k,$

where $p\sim1$ scales weakly with gate density and durations. This permits up to $k=4$ multiplexing in NISQ regimes before overhead approaches coherence-time limits for standard layouts. Grouping two-qubit couplers via graph edge-coloring allows up to four-fold multiplexing with zero overhead, bounded by circuit connectivity.

4. Circuit, Filter, and Switch Design Considerations

Filter requirements: For frequency-multiplexed lines, filter order $n$ and passband width $\Delta f$ control selectivity, with practical implementation calling for $A\geq40$ – $80\,\mathrm{dB}$ off-resonant attenuation (Shi et al., 2023).
Switching technology: Cryo-CMOS or superconducting junction switches can achieve sub-10 ns switching times, with thermal loads of $<5\,\mu$ W per switch and net mK-stage heat reduction of $50\,\mu$ W per removed line (Richter et al., 28 Aug 2025).
Channel isolation: On-chip implementation achieves $<1$ pA leakage (per channel $R_{off} \sim 30\,$ T $\Omega$ ) and crosstalk $<0.01$ dB (Bian et al., 27 Mar 2024, Al-Taie et al., 2013).
Impedance matching and cross-coupling suppression: Diplexer architectures are designed for $50\,\Omega$ matching and cross-injection of flux (e.g., $1.6\times10^{-4}\,\Phi_0$ per strong MW pulse) is suppressed so that frequency excursions are much less than the qubit linewidth (Manenti et al., 2021).

5. Analytical Models and Optimal Control under Multiplexing Constraints

Theoretical formulations extend multiplexing to networked control systems evolving on matrix Lie groups, with hard constraints that only one “plant” may receive a control signal per time step (Maheshwari et al., 2019). The associated optimal control problem incorporates nonconvex control-action constraints $U_t \in \Ustar$ (support cone of single-hot vectors), managed via Pontryagin maximum principle with auxiliary multipliers. The Hamiltonian for $M$ plants, with state, costate, and multiplexing multipliers, is

$H_t = \nu \sum_i \ell^i_t + \sum_{i=1}^M \langle \theta^i, \exp^{-1}\Gamma^i_t \rangle + \sum \langle \xi^i, f^i_t \rangle + \langle \chi, z(u^1,\dots,u^M) \rangle,$

and the necessary optimality conditions are enforced via indirect or direct transcription into an NLP. This framework is numerically tractable for small ensembles and provides a unified view of the multiplexing constraint as a component of the system Hamiltonian.

6. Practical Trade-Offs and Scalability

Multiplexing delivers quantifiable reductions in wiring, thermal load, and system complexity, but these gains are balanced by several trade-offs:

Added insertion loss and gate overhead: Each filter/diplexer step introduces 1–3 dB extra loss; serialization decreases parallelism, especially in circuits with high single-qubit gate density (Manenti et al., 2021, Richter et al., 28 Aug 2025).
Scheduling complexity: Software must manage gate alignment, serialization, and resource allocation, with critical-path analysis required to fit execution within coherence windows (Shi et al., 2023).
Fanout and crosstalk limits: Parasitic capacitances and finite line impedance bound the number of devices per control line. Typical practical limits are $M\sim20$ for spatial MUX and $k=2$ –$4$ for time-multiplexed quantum control (Bian et al., 27 Mar 2024, Richter et al., 28 Aug 2025).
Calibration and per-line tuning: Owing to disorder and layout-specific variations, crosstalk, frequency shifts, and filter detuning require in-situ calibration and, in some cases, minor hardware adaptation (e.g., air-bridges, variable capacitor trimming) (Cai et al., 4 Nov 2025, Shi et al., 2023).
Scaling pathways: For large arrays, combinations of spatial, temporal, and frequency multiplexing (potentially with optical/cryogenic interface upgrades) offer factor 10–100 effective reductions in line-count, supporting $10^3$ – $10^5$ device arrays per dilution refrigerator (Shi et al., 2023).

7. Experimental Benchmarks and Outlook

Experimental studies across platforms demonstrate that properly designed multiplexed control schemes do not inherently limit device performance:

Superconducting qubits and couplers: With combined XYZ lines, randomized benchmarking achieves $99.77\pm0.02\%$ fidelity; multiplexed DTC architectures realize $>99\%$ two-qubit gate and Bell state fidelities, $96\%$ for three-qubit GHZ, with only $15–25\%$ line-count overhead vs. non-multiplexed implementations (Manenti et al., 2021, Cai et al., 4 Nov 2025).
Cryogenic transport/MES transport: Binary-tree/address-decoder schemes attain >80% quantum yield for 256 devices in a single wire-limited cooldown (Al-Taie et al., 2013).
Time-domain photonic control: Real-time photonic sensing and feedback with 10:1 multiplexing is demonstrated at 25 Gb/s data rates with optical penalty <0.6 dB (Gaetano et al., 21 Oct 2025).
Optimal control: For small ensembles on Lie groups, single-channel multiplexing constraints are embedded in direct NLP solutions; extension to model-predictive control and convexification are promising for scalability (Maheshwari et al., 2019).

A plausible implication is that further progress in scalable control line multiplexing will require tight integration of hardware-filtering, low-loss switching, system-level calibration, and quantum circuit compilation techniques tailored to the device-level and architectural constraints of each platform.