Highly-Parallel Atom-Detection Accelerator

• The highly-parallel atom-detection accelerator is a control subsystem that uses time-pipelined and spatially parallel FPGA processing to transform optical signals into atomic state decisions.
• It employs advanced inference methods, including projection-based reconstruction and Bayesian techniques, to accurately determine atom occupancy and internal states.
• Its integrated design across optics, memory, and digital logic enables scalable, deterministic throughput crucial for efficient neutral-atom quantum computing and array assembly.

The highly-parallel atom-detection accelerator is a neutral-atom control subsystem that reduces the latency between optical readout and the control action that follows. In current literature, the term covers FPGA-based fluorescence-image reconstruction for tweezer arrays, integrated measurement-and-feedback engines for assembling defect-free atomic arrays, and optical readout architectures that expose many atom channels simultaneously. Across these realizations, the central function is to transform site-resolved optical signals into occupancy or internal-state decisions quickly enough to support rearrangement, mid-circuit measurement, and real-time feedforward (Winklmann et al., 1 Apr 2026, Wang et al., 2022, Shaw et al., 12 Jun 2025).

1. Operational setting in neutral-atom platforms

Neutral atom quantum computers are described as having long coherence times and good scalability, but their control overhead is comparatively time-consuming; one of the main contributing procedures is the detection of individual atoms and measurement of their states, each occurring at least once per compute cycle and requiring fluorescence imaging and subsequent image analysis (Winklmann et al., 3 Mar 2026). In defect-free array assembly, the same bottleneck appears in a different form: atom detection, atomic occupation analysis, rearrangement strategy formulation, and acousto-optic-deflector driving-signal generation must all be completed before the next movement step can begin, unless they are deliberately overlapped in time (Wang et al., 2022).

A highly-parallel accelerator addresses this bottleneck through two forms of concurrency. The first is temporal pipelining: Boundary Extraction, Image Extraction, Convolution, Thresholding, and Output Aggregation can operate in streaming fashion, processing different atoms in flight (Winklmann et al., 3 Mar 2026). The second is spatial parallelism: multiple multipliers or multiple tweezers operate concurrently, or multiple cavity channels are read out independently (Wang et al., 2022, Shaw et al., 12 Jun 2025).

This suggests that “acceleration” in this context is not limited to faster arithmetic. It includes architectural co-design across optics, camera interfaces, memory movement, inference kernels, and downstream control hardware.

2. Detection models and inference primitives

In fluorescence-imaging accelerators, the raw input is a camera image $I(x,y)$ in which each pixel intensity corresponds to photon counts. One implementation applies background subtraction and dark-frame correction,

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$

then determines a local region of interest for each calibrated trap center $(x_i,y_i)$ using

$${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$

with $r=15$, yielding a $31\times31$ window (Winklmann et al., 3 Mar 2026).

A projection-based reconstruction then combines the ROI with a pre-loaded point-spread-function kernel. In one formulation, the normalized projector is

$\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$

and the emission estimate is

$$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$

A global threshold $T_{\rm thr}$ produces the Boolean occupancy decision

$$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$

Optional small-cluster removal or connected-component analysis can group spurious single-pixel detections (Winklmann et al., 3 Mar 2026).

A related projection-based state-reconstruction method models the fluorescence image as

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$0

precomputes a Moore–Penrose inverse kernel $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$1 for each site, and estimates the site brightness through

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$2

followed by normalization and thresholding to “atom present/absent” (Winklmann et al., 1 Apr 2026).

When neighboring fluorescence images overlap strongly, Bayesian inference replaces direct thresholding. For a 1D register, the image model is

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$3

with likelihood

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$4

and posterior

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$5

Pure global Bayes scales as $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$6 and is intractable for $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$7, so a sliding-patch approximation updates a local posterior over $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$8 states and yields overall complexity $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$9, with $(x_i,y_i)$0–$(x_i,y_i)$1 for nearest-neighbor overlap (Martinez-Dorantes et al., 2017).

A common misunderstanding is that highly parallel detection necessarily implies a single inference method. The literature instead shows three distinct regimes: fixed-grid thresholding, projection-based reconstruction, and Bayesian inference for overlapping PSFs (Winklmann et al., 3 Mar 2026, Winklmann et al., 1 Apr 2026, Martinez-Dorantes et al., 2017).

3. FPGA architectures and hardware parallelism

The most explicit accelerator realizations are FPGA-resident dataflow pipelines. On a Xilinx UltraScale+ FPGA, one architecture comprises Boundary Extraction, Image Extraction, Kernel Preprocessing, a Convolution Engine, Thresholding, and Output Aggregation. The Convolution Engine contains a 31-wide vector multiplier array and a 5-stage binary adder tree; the entire pipeline runs at 100 MHz and produces one $(x_i,y_i)$2 and $(x_i,y_i)$3 per 35 cycles after an initial latency of approximately 200 cycles (Winklmann et al., 3 Mar 2026).

A related Xilinx Zynq UltraScale+ ZCU216 implementation organizes the reconstruction IP as a 4-stage dataflow: Boundary Extraction, Image & Kernel Fetch, Convolution, and Output Aggregation & Threshold. Because DDR bandwidth is finite and all $(x_i,y_i)$4 pixels cannot be held in BRAM, it uses a 2-deep cache so that, while stage 3 is convolving patch $(x_i,y_i)$5, stage 2 has already issued a burst read for patch $(x_i,y_i)$6. The AXI4 Master bus runs at 100 MHz with 512-bit data width, giving 6.4 GB/s peak theoretical bandwidth, and sixteen 32-bit pixels are packed into one 512-bit word (Winklmann et al., 1 Apr 2026).

The resource footprints reported for these implementations are different because the designs are not identical. One design reports LUTs $(x_i,y_i)$7, FFs $(x_i,y_i)$8, DSP48E2 $(x_i,y_i)$9, BRAM_36K $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$0, at 100 MHz, and states that resource usage is independent of $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$1 because the design time-multiplexes on a fixed ROI size and vector width (Winklmann et al., 3 Mar 2026). Another reports LUTs $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$2, FFs $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$3, DSPs $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$4, and BRAM $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$5, again emphasizing that none of these numbers grow with array size $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$6 because the $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$7 dot-product engine is time-multiplexed over all sites (Winklmann et al., 1 Apr 2026).

Implementation	Core parallel mechanism	Reported result
FPGA image reconstruction (Winklmann et al., 3 Mar 2026)	31 parallel multipliers, 5-stage adder tree, streaming dataflow	256×256 image for a 10×10 array in 115 $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$8s; throughput $${\rm ROI}_i=\{(u,v)\mid |u-x_i|\le r,\;|v-y_i|\le r\},$$9 M atoms/s
Reconstruction IP on ZCU216 (Winklmann et al., 1 Apr 2026)	4-stage dataflow, 2-deep prefetch cache, 512-bit AXI4 bursts	34.9$r=15$0 speedup over CPU-baseline and 6.3$r=15$1 over CPU-opt for 10×10
Integrated assembly pipeline (Wang et al., 2022)	5 pipelined stages on one Xilinx XCKU040 FPGA; DDS parallelism up to $r=15$2	$r=15$3s; $r=15$4 rows/s; $r=15$5 atom-flags/s for 32 columns

The significance of these architectures lies in deterministic latency. In one implementation, the per-patch timing is dominated by overlapping fetch and compute, giving a dominant per-patch cost of approximately $r=15$6s and a measured $r=15$7s for a $r=15$8 image with 100 sites (Winklmann et al., 1 Apr 2026). In another, the fixed throughput is expressed as one row every approximately $r=15$9s in the decoder pipeline (Wang et al., 2022).

4. Coupling detection to array assembly: the Tetris pipeline

The most comprehensive measurement-feedback accelerator for array assembly is the integrated FPGA system for two-dimensional defect-free atomic arrays (Wang et al., 2022). It sits between the EMCCD camera and the AODs and implements five pipelined stages on a single Xilinx XCKU040 FPGA: Photon Detection Acquisition, Image Preprocessing & Atomic Occupation Analysis, Rearrangement Strategy Computation, AOD Driving Signal Generation, and DAC Output & AOD Modulation.

The stage latencies are given explicitly. The camera contributes $31\times31$0s. The on-FPGA decoder contributes

$31\times31$1

with $31\times31$2, giving $31\times31$3s per row. The MicroBlaze processor running the Tetris algorithm contributes $31\times31$4s. The Digital Waveform Generator contributes $31\times31$5s, and the DAC contributes $31\times31$6s (Wang et al., 2022).

Because the stages overlap, the pipeline-limited row latency is

$31\times31$7

and the acquisition-to-movement startup overhead is

$31\times31$8

Once full, each additional row adds only $31\times31$9 (Wang et al., 2022).

The Tetris algorithm itself restructures row-by-row and then column-by-column in $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$0 total moves, with each move performed in full parallel across a row or column. For an $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$1 target array geometry, the number of moves scales as $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$2, the total displacement work satisfies

$\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$3

and the total rearrangement time satisfies

$\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$4

By contrast, a one-by-one Hungarian-matching approach yields $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$5 and $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$6 (Wang et al., 2022).

Measured scaling reflects both the algorithm and the pipeline. For 500 FPGA-in-the-loop trials at each $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$7, the total rearrangement time as a function of atom number $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$8 fits $\Pi(u,v)=\frac{K(u,v)}{\sum_{u,v}K(u,v)},$9 for compact geometry and $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$0 for staggered geometry. In displacement-count scaling, Hungarian on compact gives $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$1, Tetris compact gives $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$2, and Tetris stagger gives $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$3 (Wang et al., 2022).

A key corrective point is that, at large $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$4, the dominant term is not the digital pipeline but the physical atom-movement time $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$5. Highly parallel detection removes startup and planning overheads, but it does not remove the need to move atoms through space (Wang et al., 2022).

5. Experimental readout modalities

Highly parallel atom detection is not confined to one optical modality. In state-selective fluorescence readout of optically trapped $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$6Rb, a 10 ms state-detection illumination produces approximately 1100 scattered photons per Bright atom, with approximately 31 detected, while Dark atoms scatter less than or equal to 1 photon on average. Detection error by simple thresholding is approximately $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$7; Bayesian inference reduces the global error to approximately $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$8; atom survival is approximately $$E_i=\sum_{u=-r}^{r}\sum_{v=-r}^{r} I_i(u,v)\,\Pi(u,v).$$9 per detection cycle; and the reported detection fidelities exceed $T_{\rm thr}$0 within $T_{\rm thr}$1 ms while keeping $T_{\rm thr}$2 of the atoms trapped (Martinez-Dorantes et al., 2017).

Near nanophotonic devices, standard fluorescence imaging faces a different limitation: scattering from nearby photonic structures. An integrated atom-array–nanophotonic-chip platform addresses this using a multichromatic excitation and detection scheme that collects only the $T_{\rm thr}$3 nm decay, with dichroic and narrowband filters rejecting scattered $T_{\rm thr}$4 nm and $T_{\rm thr}$5 nm light. The system combines an $T_{\rm thr}$6 array of optical tweezers with a chip hosting more than 100 nanophotonic devices. In the loading region away from the chip, the single-atom detection fidelity is $T_{\rm thr}$7 at 40 ms exposure; on devices it is $T_{\rm thr}$8; residual background is less than 1 photon/pixel per 40 ms; and real-time image-processing and feedback latency is approximately $T_{\rm thr}$9s (Menon et al., 2023).

A third modality replaces camera-limited fluorescence collection with cavity-assisted parallel readout. The cavity array microscope strongly couples each individual atom to its own individual cavity across a two-dimensional array of over 40 modes. In the central 21-site subarray, the reported mean parameters are finesse $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$0, mode waist $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$1m, and peak cooperativity $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$2. With a 4 ms exposure across 21 sites, the post-processed discrimination fidelity is $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$3, atom survival during readout is greater than $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$4, and inter-site photon-count correlations satisfy $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$5 (Shaw et al., 12 Jun 2025).

These examples show that “parallel” may refer to simultaneous camera-space inference, simultaneous trap reconfiguration after image analysis, or simultaneous optical channels produced by cavity multiplexing. A plausible implication is that the accelerator concept is best understood as a control-layer abstraction rather than a single hardware block.

6. Scalability, limits, and future directions

The strongest scalability claims arise when detector and control hardware are co-designed. In the FPGA image-reconstruction architecture, the total resource usage is constant with respect to atom count because the design time-multiplexes a fixed engine; throughput is given as

$$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$6

and a $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$7 array remains in the low-ms range, with $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$8 ms reported at $$D_i= \begin{cases} 1,&E_i>T_{\rm thr},\ 0,&\text{otherwise.} \end{cases}$$9 (Winklmann et al., 3 Mar 2026). In the related ZCU216 implementation, total runtime scales proportionally to $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$00, but resource usage remains fixed because only one $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$01 engine is instantiated (Winklmann et al., 1 Apr 2026).

In the rearrangement pipeline, intersections with collective-lifetime curves give lifetime-limited maximum array sizes of approximately $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$02 atoms for compact geometry and approximately $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$03 atoms for staggered geometry at $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$04 s; greater than $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$05 atoms at $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$06 s; and, when projecting to $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$07 s, greater than $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$08 atoms (Wang et al., 2022). Further scaling is proposed through hierarchical AOD arrays, multiple FPGA↔DAC banks, time-multiplexing slower rows while the decoder processes new rows, and upgrading to UltraScale+ FPGAs with at least $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$09 DSPs (Wang et al., 2022).

The practical limits differ by platform. In the nanophotonic-chip system, AOD bandwidth limits the number of resolvable traps to approximately 80 tones, and the current maximum usable array is $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$10 because of objective field-of-view and aberrations (Menon et al., 2023). In the cavity-array platform, simultaneous mode degeneracy for thousands of modes is linked to spherical-lens-position stability $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$11m; using

$I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$12

the estimate for $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$13 and $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$14m is $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$15 (Shaw et al., 12 Jun 2025). In fluorescence-camera pipelines, DDR bandwidth is identified as the limit for larger arrays such as $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$16, motivating on-chip line buffers and multi-channel AXI interleaving (Winklmann et al., 3 Mar 2026).

Two misconceptions are repeatedly corrected by the data. First, high parallelism does not imply vanishing latency; camera exposure, EMCCD readout, and physical transport remain explicit time constants (Wang et al., 2022, Menon et al., 2023). Second, constant FPGA resource usage with respect to $I_{\rm corr}(x,y)=I(x,y)-I_{\rm dark}(x,y)-B,$17 does not imply constant total runtime; it follows from time-multiplexing fixed datapaths, so total runtime still grows with the number of sites (Winklmann et al., 3 Mar 2026, Winklmann et al., 1 Apr 2026).

The cumulative picture is that highly-parallel atom-detection accelerators now span FPGA-based fluorescence reconstruction, integrated image-to-rearrangement pipelines, background-free imaging near nanophotonic structures, and cavity-resolved readout. The shared research direction is deterministic, low-latency conversion of many optical channels into control decisions, with the eventual objective of fully integrated neutral-atom control systems that support large arrays, repeated measurement, and real-time feedback (Winklmann et al., 1 Apr 2026, Wang et al., 2022).