Cryogenic Multiplexers

• Cryogenic multiplexers are techniques for scaling low-temperature detector and quantum-device readout by minimizing wiring and parasitic heat loads.
• Implemented architectures include on-chip semiconductor routing, superconducting demultiplexers, MEMS switches, and cryoCMOS RF circuits with clearly defined scaling laws.
• These strategies enable high-throughput low-temperature metrology and quantum control through methods like frequency-division, code-domain, and charge-locking multiplexing.

Searching arXiv for recent and foundational papers on cryogenic multiplexers and related architectures. First, I’ll look for broad cryogenic multiplexer work spanning detector arrays, quantum devices, and cryogenic control. Now narrowing to microwave SQUID multiplexing, on-chip quantum-device multiplexers, and cryogenic RF switching. Cryogenic multiplexers are the set of techniques used to read out many detectors at low temperature using far fewer cables, amplifiers, and room-temperature electronics than there are physical channels. They are used because each detector or device port would otherwise require its own wiring path through the refrigerator, creating prohibitive parasitic heat load, excessive complexity, occupied volume, cooldown time, and cost. Reported implementations span gate-defined on-chip routing in semiconductor heterostructures, field-effect-transistor switch trees, superconducting demultiplexers, MEMS and cryoCMOS RF switches, FPGA-based cryogenic routing fabrics, and microwave SQUID multiplexers in which detector signals are encoded onto microwave resonators sharing a common feedline (Neidig et al., 9 Sep 2025, Paghi et al., 2024, Al-Taie et al., 2013, Lamb et al., 2015, Lee et al., 17 Jul 2025, Fallik et al., 17 Mar 2026).

1. System role and cryogenic constraints

The principal driver for cryogenic multiplexing is the I/O bottleneck. Large cryogenic detector arrays, quantum-device testbeds, and superconducting-qubit systems all confront the same constraint: room-temperature wiring scales poorly when the cold stage must host hundreds, thousands, or more channels. In magnetic microcalorimeter arrays this is especially acute because the detectors typically operate below $30\,\mathrm{mK}$ and need signal bandwidths exceeding $100\,\mathrm{kHz}$, so a scalable, low-noise, low-heat readout method is mandatory (Neidig et al., 9 Sep 2025). In superconducting quantum systems, hundreds of coax lines may already be required, while the millikelvin stage has limited physical space and very limited cooling power; one paper cites roughly $20\,\mu\mathrm{W}$ as the target budget for cryogenic multiplexers intended for large-scale quantum processors (Lee et al., 17 Jul 2025).

This common systems problem has produced several distinct multiplexing regimes. Some architectures select one device out of many for transport or DC characterization; others distribute many microwave carriers on a single feedline; others store analog control values locally and refresh them periodically; still others route RF control and readout paths directly at the qubit plane. A recurring theme is that cryogenic multiplexing is not a single circuit topology but a systems strategy in which one cold-stage interconnect, one shared feedline, or one set of shared control lines is reused across many channels (Bian et al., 2024, Wolfe et al., 2024, Bian et al., 2024).

2. On-chip semiconductor multiplexing and addressable cryogenic testbeds

A foundational class of cryogenic multiplexers uses gate-controlled depletion in semiconductor heterostructures. In GaAs/AlGaAs devices, an on-chip quantum multiplexer routes a signal through selectable depleted $2\mathrm{DEG}$ channels, enabling local device selection without changing the cryostat or requiring a separate wire for every device. This architecture was used to contact arrays of 256 split-gate devices and to measure 256 quantum wires using only 19 electrical contacts on a cryogenic set-up (Al-Taie et al., 2013, Al-Taie et al., 2014). The scaling rules were stated explicitly as

$$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$

with the important rule that adding two additional addressing gates doubles the number of output paths (Al-Taie et al., 2014).

These on-chip address networks changed the function of a cryogenic measurement chip from a single-device structure to a statistical testbed. The same platform enabled spatial mapping of pinch-off voltage, disorder statistics, cooldown-to-cooldown reproducibility, and fabrication-limited yield. One study reported a fabrication-limited yield of $94\%$, a Pearson correlation coefficient $r = 0.89$ for cooldown-to-cooldown pinch-off voltage, and disorder classification that stayed the same for $92.1\%$ of devices (Al-Taie et al., 2014). This established a major use-case for cryogenic multiplexers: not only readout compression, but also high-throughput low-temperature metrology of device variation.

Later semiconductor implementations generalized the same idea. A reconfigurable cryogenic multiplex platform based on multiple level selective gating (MLSG) separated the MUX circuitry from the quantum device under test by using a MUX PCB and a qDUT PCB connected by swappable board-to-board connectors. In the demonstrated prototype, 4 MUXs at cryogenic temperature used 14 room-temperature wires in total—10 for addressing gates and 4 for input signals—to provide 128 total interconnects (Bian et al., 2024). Its scaling relation was

$M = 2^K,$

with $N$ MUXs and $100\,\mathrm{kHz}$0 shared control lines giving $100\,\mathrm{kHz}$1 room-temperature wires and $100\,\mathrm{kHz}$2 cryogenic interconnects (Bian et al., 2024).

In Si/SiGe quantum-device technology, on-chip FET switches were used to multiplex a grid of work zones. A 16-zone chip used 4 address bits $100\,\mathrm{kHz}$3, grounded inactive zones rather than leaving them floating, and reduced wiring from 112 electrical connections to 16 electrical connections at the bond pads while operating at $100\,\mathrm{kHz}$4 and in high magnetic fields where the quantum Hall effect is observed (Wolfe et al., 2024). In a bottom-up nanowire platform, an 8-level MUX connected back-to-back to an 8-level d-MUX incorporated 1996 interconnected FETs built from selective-area-grown InAs nanowires and addressed 512 devices under test using only 37 control lines at $100\,\mathrm{kHz}$5 (Olšteins et al., 2023).

A distinct but closely related direction is the integrated on-die multiplexer for cryogenic CMOS characterization. One die contained four 1-to-1024 multiplexers, each feeding a 32 $100\,\mathrm{kHz}$6 32 farm of devices, exposing 4096 transistor positions through a small, fixed number of bond pads and enabling Kelvin-style DC characterization of thousands of transistors at $100\,\mathrm{kHz}$7 (Eastoe et al., 2024). Another control-oriented approach, the parallel refreshed cryogenic charge-locking array, used multiplexers to charge recharging capacitors and then refresh a whole row of holding capacitors in parallel. Its reported power scaling,

$100\,\mathrm{kHz}$8

and

$100\,\mathrm{kHz}$9

was contrasted with the quadratic or superlinear scaling of serial refresh; for a $20\,\mu\mathrm{W}$0 array the reported dissipation was about $20\,\mu\mathrm{W}$1 per kHz refresh rate, more than $20\,\mu\mathrm{W}$2 lower than the serially refreshed crossbar benchmark (Bian et al., 2024).

3. Superconducting, MEMS, and cryoCMOS switch multiplexers

Another major family uses cold-stage switches that route current or microwave signals directly. In a superconducting solid-state implementation, a 1-input-8-outputs voltage-actuated hybrid superconducting demultiplexer was realized with 14 ON/OFF InAsOI-based superconducting Josephson Field Effect Transistors routed with Al traces. At $20\,\mu\mathrm{W}$3, the device operated up to $20\,\mu\mathrm{W}$4, had insertion loss of $20\,\mu\mathrm{W}$5 in the superconducting state, and an OFF/ON ratio of $20\,\mu\mathrm{W}$6 in a $20\,\mu\mathrm{W}$7-Ohm-matched cryogenic measurement setup (Paghi et al., 2024). Because the circuit is reciprocal, it can in principle be used as a multiplexer simply by swapping the input/output roles. Its architecture followed the combinatorics

$20\,\mu\mathrm{W}$8

for the number of JoFETs and output paths (Paghi et al., 2024).

MEMS switches provide a different route to cryogenic RF multiplexing. Commercial SP4T RF MEMS switches were evaluated at approximately $20\,\mu\mathrm{W}$9, where the measured pull-in voltage decreased by about $2\mathrm{DEG}$0, the on-resistance decreased by about $2\mathrm{DEG}$1, insertion loss remained below $2\mathrm{DEG}$2 in the $2\mathrm{DEG}$3–$2\mathrm{DEG}$4 qubit band, and isolation exceeded $2\mathrm{DEG}$5 (Lee et al., 17 Jul 2025). Stable SP4T switching and logical operations, including NAND and NOR gates, were demonstrated at cryogenic temperatures, and no observable performance degradation was reported after more than 100 million cycles. A notable limitation was severe bouncing at $2\mathrm{DEG}$6, persisting for about $2\mathrm{DEG}$7, which was mitigated by a dual-pulse engineered gate waveform (Lee et al., 17 Jul 2025).

Superconducting microwave switching can also be used for multiplexing protocols rather than static path selection. The Tunable Inductor Bridge is a broadband two-port microwave circuit element with three modes of operation—transmit, reflect, and invert—over $2\mathrm{DEG}$8–$2\mathrm{DEG}$9, with switching $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$0, on-off ratio $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$1 across the full band, and insertion loss below $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$2 for the devices used in the multiplexing experiment (Chapman et al., 2016). In a two-channel code-domain multiplexing demonstration, multiplexed data were recovered with readout times up to $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$3 and infidelities less than $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$4 for probe powers greater than $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$5, in agreement with binary signaling with Gaussian noise (Chapman et al., 2016).

Millikelvin cryoCMOS RF multiplexing extends the same concept into foundry CMOS. A 22 nm FDSOI SP4T RF multiplexer operating at $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$6 reported static power consumption of $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$7, insertion loss $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$8, and isolation $$N_{2mux}=2^{(n-1)/2}, \qquad N_{3mux}=2^{(n-1)/2}+2^{(n-3)/2},$$9 across DC-8 GHz (Fallik et al., 17 Mar 2026). Direct connection to transmon qubits marginally affected coherence times in the range of 100 microseconds, enabling multiplexing of readout, flux and, in principle, XY drive lines. The main caveat was flux-line Joule heating: at the largest flux bias used, $94\%$0 through an on-state resistance of about $94\%$1 dissipated about $94\%$2, raised the mixing chamber temperature by up to $94\%$3, and reduced $94\%$4 by about $94\%$5 away from the sweet spot (Fallik et al., 17 Mar 2026).

4. Microwave SQUID multiplexers and hybrid detector readout schemes

For cryogenic detector arrays, microwave SQUID multiplexing ($94\%$6MUX) is a dominant architecture, and in magnetic microcalorimeter readout it is described as the state of the art (Neidig et al., 9 Sep 2025). Its basic principle is frequency-division multiplexing in the microwave domain: each detector is inductively coupled to a non-hysteretic rf-SQUID, the rf-SQUID is coupled to a superconducting microwave resonator with a unique resonance frequency, and many resonators share a common feedline. A detector event changes the magnetic flux threading the SQUID loop, the SQUID’s effective inductance changes, and the resonance frequency of that channel’s resonator shifts. By probing each resonator with a continuous microwave carrier and monitoring the transmitted amplitude and/or phase, many channels can be interrogated simultaneously over one line (Neidig et al., 9 Sep 2025).

A full-scale MMC-oriented implementation combined a custom $94\%$7MUX chip with custom software-defined radio electronics and was explicitly capable of handling up to 400 channels (Neidig et al., 9 Sep 2025). The chip contained eighteen coplanar-waveguide quarter-wave resonators spanning $94\%$8 to $94\%$9, covering the target $r = 0.89$0–$r = 0.89$1 operating band. The rf-SQUIDs were designed to be non-hysteretic with

$r = 0.89$2

corresponding to $r = 0.89$3 and $r = 0.89$4 (Neidig et al., 9 Sep 2025). Flux-ramp modulation linearized the inherently nonlinear SQUID response; in the reported experiment the ramp had amplitude $r = 0.89$5 and repetition rate $r = 0.89$6, with an effective ramp amplitude of $r = 0.89$7 used for demodulation (Neidig et al., 9 Sep 2025).

The measured performance was broadband and low-noise. Open-loop white noise stayed below $r = 0.89$8 across the full $r = 0.89$9–$92.1\%$0 band, with a mean of $92.1\%$1. With flux-ramp demodulation enabled, the average white noise became $92.1\%$2, and all channels remained below $92.1\%$3 except one outlier caused by an incorrect demodulation-frequency setting (Neidig et al., 9 Sep 2025). The paper attributes the increase to the expected flux-ramp penalty factor

$92.1\%$4

with $92.1\%$5, and to additional broadening from non-ideal sinusoidal modulation of the readout tone amplitude (Neidig et al., 9 Sep 2025). No measurable difference in noise performance was observed between channels connected to MMCs and channels without detectors, suggesting that microwave leakage into the MMC sensors was not significantly degrading the readout in that setup (Neidig et al., 9 Sep 2025).

Related $92.1\%$6MUX work optimized for TES bolometers reported a scalable 1820-channel configuration in the 4–8 GHz rf band, with 65 readout channels per die, minimum designed frequency spacing of $92.1\%$7, median white-noise level of $92.1\%$8 evaluated at $92.1\%$9, $M = 2^K,$0 knee of about $M = 2^K,$1 after common-mode subtraction, and measured crosstalk between any channel pair $M = 2^K,$2 (Dober et al., 2020). In MMC readout specifically, a tailored $M = 2^K,$3MUX system demonstrated simultaneous readout of up to 8 multiplexer channels, corresponding to 16 detector pixels, with baseline energy resolution about $M = 2^K,$4, resolution at $M = 2^K,$5 about $M = 2^K,$6–$M = 2^K,$7, and crosstalk well below $M = 2^K,$8 (Richter et al., 2022).

Hybrid schemes extend conventional one-resonator-per-SQUID $M = 2^K,$9MUX. The hybrid microwave SQUID multiplexer coupled multiple SQUIDs to a common readout resonator and encoded the SQUID input signals in sidebands of the microwave carrier by varying the flux-ramp modulation frequency for each SQUID; the paper argued by means of fundamental information theory that the method is particularly suited for reading out large cryogenic bolometer arrays (Schuster et al., 2022). The impedance-modulated code-division multiplexer combined $N$0MUX with Walsh code-division multiplexing, assigning multiple rf-SQUIDs to each resonator and proposing $N$1–$N$2 detectors per coaxial cable pair for low-bandwidth detector applications (Yu et al., 2020). These results show that the resonator count itself is now a design variable rather than a fixed one-channel-per-resonator rule.

5. Readout electronics, emulation, and auxiliary multiplexed instrumentation

Cryogenic multiplexers are inseparable from the room-temperature and intermediate-stage electronics that generate probe tones, digitize responses, and perform real-time demultiplexing. In the full-scale MMC $N$3MUX system, the room-temperature readout was a custom SDR-based data-acquisition system optimized for the $N$4–$N$5 band. The receive side downconverted the $N$6-wide microwave band into five complex baseband signals, each with $N$7 bandwidth, digitized them with dual-channel ADCs at $N$8, and processed them in real time on the FPGA. The transmit side used three four-channel DACs at $N$9 to synthesize the probe tones, while two additional DACs generated the sawtooth waveform for flux-ramp modulation. The firmware performed digital downconversion, channelization, flux-ramp demodulation, and triggering, and could be configured at runtime (Neidig et al., 9 Sep 2025).

Testing such systems is itself a multiplexing problem because the cryogenic resonators and SQUIDs are part of the signal encoding chain. CryoDE addressed this by emulating detector pulse generation, RF-SQUID response, and carrier modulation for microwave SQUID multiplexed systems, enabling full hardware-in-the-loop testing of room-temperature DAQ firmware without requiring the cryogenic hardware (Muscheid et al., 5 Dec 2025). In the reported ECHo-100k evaluation, four CryoDE instances were integrated into the firmware, the event distribution roughly followed the expected Poisson distribution, the demodulated pulse agreed well with the generated one with residual deviation less than $100\,\mathrm{kHz}$00, and the reported error metrics were RMSE $100\,\mathrm{kHz}$01, MAE $100\,\mathrm{kHz}$02, and $100\,\mathrm{kHz}$03 (Muscheid et al., 5 Dec 2025).

Deeper inside the cryostat, digital routing can also be placed near the experiment. A modular motherboard plus daughterboard architecture centered on a Xilinx Artix-7 FPGA demonstrated cryogenic operation approaching $100\,\mathrm{kHz}$04, enabling signal routing, multiplexing, and complex digital signal processing close to the device or detector (Lamb et al., 2015). Digital logic, block RAM, and DSP slices were operational; the maximum frequency at $100\,\mathrm{kHz}$05 was $100\,\mathrm{kHz}$06 at $100\,\mathrm{kHz}$07, compared with $100\,\mathrm{kHz}$08 at $100\,\mathrm{kHz}$09, while PLLs were non-operational (Lamb et al., 2015). This suggests that cryogenic multiplexing can be implemented not only as passive or analog circuitry but also as a configurable digital routing layer.

The concept also extends beyond readout to cryogenic laboratory instrumentation. A scalable cryogenic LED module for kinetic inductance detector arrays used a two-dimensional row/column shift-register multiplexer requiring seven wires to control 480 red LEDs arranged as 20 rows $100\,\mathrm{kHz}$10 24 columns, with demonstrated operation at $100\,\mathrm{kHz}$11 and $100\,\mathrm{kHz}$12 (Shroyer et al., 2022). Although this is a special-purpose illumination system rather than a detector readout chain, it shows that cryogenic multiplexing also functions as an instrumentation method for mapping, stimulation, and in-cryostat control.

6. Applications, limitations, and scaling outlook

Cryogenic multiplexers are now used across several application domains. In cryogenic detector science they enable large MMC and TES arrays for neutrino-mass measurements, X-ray imaging spectroscopy, cosmic microwave background polarization measurements, and bolometric astronomy (Muscheid et al., 5 Dec 2025, Dober et al., 2020). In mesoscopic and quantum-device research they turn low-temperature chips into large-scale statistical testbeds for yield analysis, disorder studies, and reproducibility measurements (Al-Taie et al., 2013, Al-Taie et al., 2014). In superconducting and semiconductor quantum computing they address the wiring bottleneck for readout, flux biasing, microwave control, and high-throughput characterization (Wolfe et al., 2024, Fallik et al., 17 Mar 2026).

Several misconceptions are clarified by the literature. First, cryogenic multiplexing is not synonymous with time-division switching: frequency-division, code-domain, charge-locking, row/column scanning, and passive optical or sub-THz multiplexed links all appear in reported systems (Neidig et al., 9 Sep 2025, Chapman et al., 2016, Bian et al., 2024, Shroyer et al., 2022, Succar et al., 30 Sep 2025). Second, the dominant limitation is often not the multiplexing concept itself. In the full-scale MMC $100\,\mathrm{kHz}$13MUX experiment, the main practical limitation encountered was available drive power: the DAC output power together with the $100\,\mathrm{kHz}$14 cryogenic attenuation was insufficient to optimally drive all 400 tones simultaneously (Neidig et al., 9 Sep 2025). In the tailored MMC $100\,\mathrm{kHz}$15MUX demonstration, degraded resonator internal quality factor $100\,\mathrm{kHz}$16 and reduced per-tone power, rather than the multiplexing principle, limited the co-added energy resolution (Richter et al., 2022). In MLSG-based cryogenic transport measurements, positive bias on inactive addressing gates was required because otherwise the MUX channel could saturate and produce current plateaus that might be mistaken for intrinsic device physics (Bian et al., 2024). In cryogenic MEMS, stable switching required waveform engineering because packaging dynamics caused severe bouncing at low temperature (Lee et al., 17 Jul 2025).

The scaling outlook has therefore broadened from cold-stage wiring reduction to full cryogenic interconnect architectures. An all-passive cryogenic high-frequency direct-detection control platform proposed multiplexed photonic or sub-THz receivers at $100\,\mathrm{kHz}$17 as a classical interface for direct qubit control (Succar et al., 30 Sep 2025). For the photonic WDM case, the paper estimated that existing $100\,\mathrm{kHz}$18 cooling power at $100\,\mathrm{kHz}$19 could support about 7500 qubits using 1875 fibers carrying 4 channels each; with photodiode responsivity improved toward $100\,\mathrm{kHz}$20, the same architecture could support on the order of 30,000 qubits; if qubit operating temperature is raised to around $100\,\mathrm{kHz}$21, the relaxed thermal noise floor could enable hundreds of thousands of qubits; and with about $100\,\mathrm{kHz}$22 of $100\,\mathrm{kHz}$23 cooling, millions of qubits were suggested as a longer-term possibility (Succar et al., 30 Sep 2025). This suggests that future cryogenic multiplexers will be judged not only by channel count, insertion loss, or flux noise, but by how effectively they integrate switching, encoding, local storage, and cold-stage power management into a scalable cryogenic systems architecture.