SRAM-based Physically Unclonable Function

• SRAM-based PUFs are silicon security mechanisms that exploit inherent start-up biases in SRAM cells to generate unique, device-specific fingerprints.
• They leverage standard on-chip SRAM without additional circuitry, making them ideal for low-cost implementations in MCUs, SoCs, and FPGAs.
• Advanced techniques like fuzzy extractors and error correction mitigate noise, temperature, and aging effects to ensure reliable cryptographic key extraction.

An SRAM-based physically unclonable function (PUF) is a silicon PUF that derives a device-specific response from the biased power-up state of conventional SRAM cells. In the standard abstraction, the SRAM address acts as the challenge and the start-up bit value acts as the response; the aggregate start-up image over many cells forms a hardware-intrinsic fingerprint that can be used for identification, authentication, and on-demand key generation without custom PUF circuitry. Because SRAM is already embedded in commodity microcontrollers, SoCs, FPGAs, and related platforms, SRAM PUFs are among the most widely studied low-cost hardware roots of trust (Gao et al., 2017, Gao et al., 2019).

1. Physical mechanism and PUF model

The canonical SRAM PUF is built on the start-up behavior of the 6T SRAM cell. A cell consists of two cross-coupled inverters and two access transistors; at power-up, minute mismatch in transistor threshold voltages and related device parameters breaks the ideal symmetry, so one side of the latch wins the regenerative race and the cell settles to a preferred logic value. In the formulation used for commodity SRAM PUFs, if one pMOS threshold is smaller than its cross-coupled counterpart, the corresponding side conducts first and the cell prefers one stable state; the magnitude of that mismatch determines how reliably the preference survives noise and environmental variation (Gao et al., 2017).

This mechanism makes SRAM PUFs a paradigmatic weak PUF. The challenge space is limited, often to address selection or region selection, but the response is highly instance-specific because the underlying mismatch pattern is induced by uncontrollable fabrication variation. Addressable formulations remain common: an SRAM address, or a selected set of addresses, specifies which cells are read, while the resulting power-up bits constitute the response vector (Gao et al., 2017, Mohammadinodoushan, 2020).

A practical condition is that the SRAM must be truly depowered before evaluation. On embedded MCUs, a reset is often insufficient because SRAM contents persist across system reset; a full power cycle is required to re-expose the physical start-up pattern. This was emphasized in measurements on STM32 microcontrollers, where USB power had to be physically removed to obtain fresh SRAM PUF responses (Zeinzinger et al., 16 Mar 2026).

2. Statistical characterization and quality metrics

SRAM PUF evaluation is usually organized around Hamming-distance-based metrics. For two bit vectors $\mathbf{X}_1,\mathbf{X}_2$ of length $l$, the Hamming distance and fractional Hamming distance are

$$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$

Intra-device distances quantify reproducibility under repeated measurements on the same chip, while inter-device distances quantify uniqueness across chips (Gao et al., 2017).

For aging studies, the distinction is refined further into intraA-distance, comparing repeated pre-aging evaluations, and interA-distance, comparing pre-aging and post-aging responses. In the cited treatment both are modeled as binomial random variables $B(n,p)$, with $\hat p_{\rm intraA}$ representing baseline noise-induced unreliability and $\hat p_{\rm interA}$ representing aging-induced unreliability (Gao et al., 2017).

Large-scale field measurements on 708 IoT nodes with 64 kB SRAM provide a broader statistical picture. Across devices, the average inter-device Hamming distance per 1 kB block was approximately $0.48$, close to the ideal $0.5$, while intra-device distance was approximately $0.06$. The same study reported inter-device min-entropy per bit of about $0.75$ and intra-device min-entropy per bit of about $l$0, showing that SRAM simultaneously contains stable identity structure and usable noise for seed derivation (Kietzmann et al., 2023).

Temperature-focused characterization on embedded STM32 platforms used majority-voted reference fingerprints and fractional Hamming distance to separate reliability from uniqueness. In that setup, a known fingerprint $l$1 was built from 50 measurements at $l$2, and later fingerprints were compared to $l$3 by FHD. The methodology distinguished intra-class distance, reflecting repeated measurements of the same device, from inter-class distance between different devices, and showed that two closely related MCUs can have materially different SRAM PUF quality despite sharing the same process node (Zeinzinger et al., 16 Mar 2026).

3. Reliability limits: temperature, voltage, and aging

SRAM PUF reliability is fundamentally bounded by thermal noise, supply variation, temperature dependence, and transistor aging. Several studies in the corpus converge on the observation that temperature dominates voltage as the main environmental stressor. On MSP430FR5969 CRFID platforms, reliability was reported to be much less sensitive to voltage variation than to temperature fluctuation, motivating temperature-centered enrollment and reconstruction strategies (Gao et al., 2019). On chipKIT Pro MX7 microcontrollers, voltage variation between 3.125 V and 3.50 V had negligible impact on reliability, consistent with earlier work, while temperature dependence remained visible (Gao et al., 2017).

The comparative STM32 study quantified this effect directly over $l$4, $l$5, and $l$6. For STM32F401RE, average intra-device FHD relative to a $l$7 reference was $l$8, $l$9, and $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$0 at $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$1, $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$2, and $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$3, respectively; for STM32F446RE, the corresponding values were $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$4, $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$5, and $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$6. This indicates that even closely related SRAM macros can differ substantially in temperature robustness, and that enrollment temperature strongly conditions later reconstruction cost (Zeinzinger et al., 16 Mar 2026).

Aging introduces a second, slower reliability failure mode. In SRAM PUF cells, negative bias temperature instability can shift pMOS thresholds over time so that a previously stronger device becomes weaker, potentially inverting the cell’s preferred start-up state. One study quantified an acceleration factor of approximately $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$7 for stress at $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$8 relative to $$f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)=\sum_{i=1}^{l} \mathbf{X}_1 \oplus \mathbf{X}_2, \qquad f_{\rm FHD}(\mathbf{X}_1,\mathbf{X}_2)=\frac{f_{\rm HD}(\mathbf{X}_1,\mathbf{X}_2)}{l}.$$9, so that 48 hours at $B(n,p)$0 approximated 22.1 days of normal aging. Rather than treating this only as a defect, the same work exploited aging-sensitive SRAM bits as a zero-cost recycling detector, showing that with carefully selected aging-sensitive responses and $B(n,p)$1 repeated RT/HT measurements, $B(n,p)$2 bits were sufficient for $B(n,p)$3, supporting the claim that fewer than 1,000 SRAM responses suffice to guarantee both FAR and FRR no more than 0.001 (Gao et al., 2017).

This suggests a bifurcation in SRAM-PUF engineering. Classical key-generation designs seek to suppress unstable bits and aging drift, whereas supply-chain security designs can intentionally amplify and classify the same phenomena.

4. Key extraction, helper data, and error correction

Because raw SRAM responses are noisy, cryptographic key generation almost always uses a fuzzy extractor or secure-sketch construction. In the syndrome-based formulation, an enrolled response $B(n,p)$4 is mapped to helper data $B(n,p)$5 for a linear ECC with parity-check matrix $B(n,p)$6; reconstruction uses a noisy $B(n,p)$7, computes the syndrome of the error pattern, corrects it, and then hashes the recovered response to derive the key (Gao et al., 2019). Code-offset constructions of the form $B(n,p)$8 are also standard, particularly in SRAM PUF practice (Müelich et al., 2017).

The coding literature on SRAM PUFs is broad. A polar-code construction generated 128-bit keys from 1024 SRAM-PUF bits with 896 helper data bits and achieved a failure probability of $B(n,p)$9 or lower at practical bit error probability $\hat p_{\rm intraA}$0 by combining successive cancellation list decoding with hash-based checking (Chen et al., 2017). Convolutional-code-based extraction showed that soft information, list decoding, and larger memory length can substantially reduce reconstruction failure; for example, a rate-$\hat p_{\rm intraA}$1 code with $\hat p_{\rm intraA}$2, list size $\hat p_{\rm intraA}$3, and three readouts achieved $\hat p_{\rm intraA}$4 for $\hat p_{\rm intraA}$5, $\hat p_{\rm intraA}$6 for $\hat p_{\rm intraA}$7, and below $\hat p_{\rm intraA}$8 for $\hat p_{\rm intraA}$9 and $\hat p_{\rm interA}$0 while using all response bits (Müelich et al., 2017).

Resource-constrained devices motivate architectural refinements. Reverse fuzzy extractors move the computationally heavy reconstruction step to a server, leaving only syndrome generation and hashing on the token. On MSP430FR5969 CRFID devices, combining reverse fuzzy extraction with multiple reference responses enrolled at different temperatures reduced token-side overhead from about 1,211,461 clock cycles to about 617,470 clock cycles while still achieving $\hat p_{\rm interA}$1 with BCH(63,16,11) over 8 blocks (Gao et al., 2019).

Recent lightweight schemes push more burden into bit selection rather than stronger ECC. A beat-sensor design on STM32 Cortex M0+ devices selected highly stable bits from a 120,000-bit SRAM image using a weighting-and-threshold method. With threshold $\hat p_{\rm interA}$2, the selected 128-bit response exhibited at most one flipped bit under the tested temperature and aging conditions, allowing a Hamming-code fuzzy extractor and SHA-256 to derive a 256-bit key with low on-device cost (Pham et al., 10 Aug 2025). A related threshold-authentication study on ESP32-S3 IIoT nodes combined Hamming-code error correction with temporal majority voting, showed that more redundancy and more voting reduced BER with diminishing returns, and reframed the threshold gap between FRR and FAR constraints as an error-constrained design budget for tuning response length, stabilization, and acceptance threshold (Lehn et al., 17 Apr 2026).

5. Authentication, key management, and system integration

SRAM-based PUFs support several distinct deployment patterns. The most established is device authentication and key generation. Proof-of-concept systems on external Cypress SRAM with Arduino-class controllers used ternary classification of cells into stable 0, stable 1, and unstable X, reducing raw error from approximately 3–5% to approximately 1% after four enrollment cycles, below 0.1% after 25 cycles, approximately 0.05% after 50 cycles, and approximately 0.01% after 1000 cycles. The same line of work compared BCH- and polar-based fuzzy extractors and highlighted the trade-off between false rejection and false acceptance under stronger error correction (Korenda et al., 2019).

A second pattern is application-specific secret derivation. In an addressable PUF generator for password management, SHA2-256 of a password was expanded into 128 addresses over an 8 KB SRAM PUF region, fuzzy cells were skipped using a ternary map, and the resulting 128 selected cells yielded a 128-bit PUF response bound jointly to the password and the device. The architecture relied on repeated enrollment reads, a masking block, and the fact that the PUF secret is regenerated rather than stored (Mohammadinodoushan, 2020).

A third pattern is operating-system integration. RIOT OS integrated SRAM PUF services across about 250 platforms and grounded the design in measurements from more than 700 naturally aged IoT nodes. On COTS devices with 64 kB SRAM, secure random seeds derived from the SRAM PUF were reported to provide 256 bits of security, and device-unique keys more than 128 bits of security. The implementation inserted PUF processing into the reset path before SRAM initialization, managed soft-reset detection, derived general-purpose and secure seeds, reconstructed keys with helper data, and then erased raw PUF material from normal memory (Kietzmann et al., 2023).

Finally, SRAM PUFs can act as non-cryptographic sensors. The aging-sensitive-response method repurposed commodity SRAM as an embedded aging monitor for detecting recycled SoCs, requiring no additional on-chip hardware and directly targeting supply-chain security for recycled or remarked components (Gao et al., 2017).

6. Variants, extensions, and adjacent research directions

The classical SRAM PUF uses digital start-up states of standard SRAM macros, but several adjacent directions extend or reinterpret the concept. A design-time study introduced two cell-level metrics for estimating reliable SRAM-PUF cells before fabrication: a weighted mismatch factor based on transistor threshold-voltage mismatch and a separatrix intersection distance derived from the cell’s dynamical state space. The two metrics were strongly correlated with $\hat p_{\rm interA}$3; when selecting 256 bits, SID-based ranking yielded 98.8% cells that were both temperature-stable and 100% repeatable under the paper’s noise model, compared with 30.9% under random selection (Alheyasat et al., 2024).

At the architectural level, a memory-based combination PUF coupled SRAM start-up values with DRAM refresh-pause behavior through XOR and SHA-256. Under the paper’s challenge model, the combined CRP space scaled from roughly $\hat p_{\rm interA}$4 for a side-by-side design to roughly $\hat p_{\rm interA}$5 for the coupled construction, and authentication tests across $\hat p_{\rm interA}$6 to $\hat p_{\rm interA}$7 and 12 months of accelerated aging reported 100% true-positive and 0% false-positive rates (Sutar et al., 2017).

Other works depart more substantially from the classical model. An adaptive multi-bit SRAM-topology-based analog PUF used a 16×16 array of SRAM-like analog cells, a current-mirror array, and a configurable single-slope ADC with 6–8 bit adaptive quantization; the reported implementation consumed 306.54 $\hat p_{\rm interA}$8W at 6.4 GHz and 0.0478 pJ per cycle for the proposed PUF, but this is an SRAM-topology analog PUF rather than a standard power-up SRAM PUF (Sharma et al., 2019). SRAM-SUC, by contrast, replaced repeated analog PUF evaluation with an internally generated digital cipher stored in SRAM blocks on SoC FPGAs, achieving 2.88 $\hat p_{\rm interA}$9s and 0.72 $0.48$0s response generation at 50 MHz and 200 MHz, respectively; it was explicitly framed as a digital alternative to some reliability limitations of conventional PUFs (Mars et al., 2021).

Commodity-system investigations show that SRAM-PUF observability is platform-dependent. A study of large CPUs and GPUs found no usable intrinsic SRAM PUF in the tested AMD64 CPU registers or caches because those structures were deterministically initialized before software could observe them, whereas Nvidia GTX 295 shared memory exposed a usable SRAM PUF (Aubel et al., 2015). This contrast underscores a broader point: SRAM PUF behavior is not merely a property of cells, but of the entire boot, reset, and access path.

SRAM-based PUFs therefore occupy a broad design space. At one end lie weak, low-cost silicon fingerprints extracted from conventional on-chip SRAM for keys and identities; at the other lie hybrid, analog, or digitally mediated constructions that use SRAM topology, SRAM storage, or SRAM start-up statistics as one component in a richer security mechanism. Across that range, the central engineering problem remains consistent: identify which aspects of SRAM variability should be suppressed for reproducibility, and which should be preserved or amplified for security.