SiMRA: Simultaneous Multi-Row DRAM Activation

• SiMRA is a DRAM technique that intentionally activates multiple rows simultaneously, enabling analog summing for majority computation and digital in-memory operations.
• It leverages aggressive timing violations in commodity DDR4 to perform in-memory logic, trigger true random number generation, and support device-specific signature generation.
• Empirical studies demonstrate that increased activation widths enhance success rates and entropy, while device variability and interference shape performance and reliability.

Simultaneous Multiple-Row Activation (SiMRA) denotes the intentional concurrent activation of more than one memory row within the same subarray, such that multiple cells connected to each bitline participate in a single sensing event. In commodity DDR4 DRAM, SiMRA is typically realized by deliberately violating the timing constraints of an ACT→PRE→ACT sequence, allowing 2, 4, 8, 16, or 32 rows to remain effectively open at once; in asymmetric dual-row activation (ADRA), the same concept is adapted to dual-row current sensing with unequal wordline biases. Across the literature, SiMRA serves as a substrate for in-memory majority computation, arbitrary two-operand digital computing-in-memory (CiM), true random number generation, and device-specific signature generation, while also exposing new failure modes related to analog interference and timing-dependent robustness (Olgun et al., 2021, Yuksel et al., 2024, Malhotra et al., 2022).

1. Physical basis and sensing models

In conventional DRAM operation, each cell is a capacitor-access-transistor pair connected at the intersection of a wordline and a bitline. At idle, the bitline is precharged to $V_{DD}/2$. When a single row is activated, the accessed cell shares charge with its bitline, creating a small perturbation, commonly written as $V_{BL}=V_{DD}/2 \pm \Delta V$, after which the sense amplifier (SA) detects the sign of the perturbation and restores the bitline to a full logic level. SiMRA modifies this regime by connecting multiple cells on the same bitline in parallel before the SA resolves the state, so the sensed quantity becomes the sum of several charge-sharing contributions rather than one (Olgun et al., 2021).

For $N$ simultaneously activated rows, the literature expresses the bitline voltage as a function of the aggregate stored charge. One formulation is

$$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$

where $k$ is the number of activated cells that initially store logic “1.” When $k \approx N/2$, the residual perturbation approaches the SA’s metastability window, so thermal noise, device mismatch, and timing skew can make the final resolution fundamentally unpredictable. In contrast, when the aggregate perturbation is sufficiently above or below the sensing threshold, the same mechanism yields deterministic computation, notably majority evaluation (Yuksel et al., 23 Oct 2025).

The computational interpretation follows directly from the sensing threshold. In many-row DRAM SiMRA, the output is

$OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$

so the activated rows implement an $M$-input majority operator. This is the basis for MAJ3, MAJ5, MAJ7, and MAJ9 operations in off-the-shelf DRAM, as well as for row-copy and bulk-write primitives that exploit the SA’s broadcast behavior after multi-row activation (Yuksel et al., 2023).

A distinct but related formulation appears in ADRA. There, two rows are activated simultaneously but with different wordline voltages, $V_{GREAD1}$ and $V_{GREAD2}$, with $V_{BL}=V_{DD}/2 \pm \Delta V$0. The sensed bitline current becomes

$V_{BL}=V_{DD}/2 \pm \Delta V$1

producing four distinct current levels for $V_{BL}=V_{DD}/2 \pm \Delta V$2. This removes the many-to-one ambiguity of symmetric dual-row activation and enables direct sensing of $V_{BL}=V_{DD}/2 \pm \Delta V$3, $V_{BL}=V_{DD}/2 \pm \Delta V$4, and one operand bit, from which arbitrary Boolean functions, subtraction, and comparison are reconstructed (Malhotra et al., 2022).

2. Realization in commodity DDR4

The canonical DRAM implementation of SiMRA uses an ACT→PRE→ACT sequence with deliberately reduced $V_{BL}=V_{DD}/2 \pm \Delta V$5 and $V_{BL}=V_{DD}/2 \pm \Delta V$6. QUAC-TRNG gives a concrete four-row example: issue ACT to Row$V_{BL}=V_{DD}/2 \pm \Delta V$7, wait less than $V_{BL}=V_{DD}/2 \pm \Delta V$8, issue PRE, wait less than $V_{BL}=V_{DD}/2 \pm \Delta V$9, then ACT Row$N$0. Because the PRE has not completed, the second ACT effectively re-opens the first row; combined with the hierarchical wordline structure and a two-bit least-significant-bit decoder, this causes Rows 0, 1, 2, and 3 to open together. When these rows store conflicting data, the net bitline deviation

$N$1

can fall below the reliable sensing margin, pushing the SA into metastable resolution (Olgun et al., 2021).

Later characterization generalized this mechanism from four-row activation to simultaneous activation of 2, 4, 8, 16, and 32 rows. The key decoder hypothesis is that the first ACT and the second ACT leave multiple predecoder outputs latched before reset, so the local decoder drives all wordlines consistent with both address sets. In the characterized 4 Gb $N$28 DDR4 chips, the number of retained predecoder tiers was reported as $N$3, enabling up to $N$4 simultaneously activated rows (Yuksel et al., 2024).

The timing regime is aggressive. In the 2024 characterization, SiMRA used $N$5–$N$6 ns in place of the nominal ACT-to-PRE interval of roughly $N$7 ns, and $N$8 ns instead of the nominal PRE-to-ACT interval of roughly $N$9 ns; all other timing parameters remained at or above JEDEC minima. The same study reported that with $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$0, SiMRA activates $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$1 rows with $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$2 (Yuksel et al., 2024). The 2026 PUF study reports nominal DDR4-3200 timings of $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$3 ns and $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$4 ns, while noting that successful SiMRA experiments often reduce both values to well below $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$5 ns (Baser et al., 13 Jun 2026).

Reliable manifestation is vendor- and revision-dependent rather than universal. In the 2025 TRNG study, 152 DDR4 chips from SK Hynix, Samsung, and Micron were tested, but only SK Hynix chips reliably exhibited SiMRA; the study therefore focused on 96 SK Hynix chips. The 2026 PUF study similarly tested 144 DDR4 chips from SK hynix, Samsung, and Micron and reported reliable SiMRA only in 112 SK hynix chips (Yuksel et al., 23 Oct 2025, Baser et al., 13 Jun 2026). This is central to the present state of the field: SiMRA has been demonstrated on unmodified commercial hardware, but not as a vendor-independent JEDEC-guaranteed operation.

3. Computational primitives and CiM formulations

In DRAM-based processing-using-memory, SiMRA is primarily a majority primitive. The 2024 experimental characterization showed that off-the-shelf DDR4 chips can execute MAJ3, MAJ5, MAJ7, and MAJ9, as well as copy one row concurrently to up to 31 other rows, termed Multi-RowCopy. For random data and best timings $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$6, the reported MAJ3 success rates were $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$7 for 4-row activation, $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$8 for 8-row activation, $$V_{BL} \simeq V_{DD}/2 + (2k-N)\cdot (C_{cell}/C_{BL})\cdot (V_{DD}/2),$$9 for 16-row activation, and $k$0 for 32-row activation. At 32-row activation, the reported success rates were approximately $k$1 for MAJ5, $k$2 for MAJ7, and $k$3 for MAJ9 (Yuksel et al., 2024).

A central design principle is operand replication. Instead of activating exactly the number of rows implied by the Boolean arity, later work stores multiple copies of each operand across the simultaneously activated rows, with leftover rows neutralized. For MAJ3 using 32-row activation, each input can be replicated 10 times with two neutral rows. This increases the effective sensing margin. The 2024 characterization reports that MAJ3 with 32-row activation has a $k$4 higher average success rate than MAJ3 with 4-row activation, while PULSAR reports that 32-row replication yields approximately $k$5 higher $k$6 than 4-row FracDRAM in SPICE Monte Carlo and achieves an average $k$7 success rate on MAJ3, compared with $k$8 for FracDRAM, a $k$9 absolute improvement (Yuksel et al., 2024, Yuksel et al., 2023).

PULSAR extends the primitive set beyond majority evaluation. It introduces Multi-RowInit, in which one source row is copied into multiple destination rows by exploiting the fact that after a multi-row ACT/PRE/ACT sequence the SA can restore the same sensed value into all activated rows. It also introduces Bulk-Write, where a single WRITE after multi-row activation drives the new data into all participating rows. On seven bit-serial logic and arithmetic kernels—AND, OR, XOR, ADD, SUB, MUL, and DIV—PULSAR reports a $k \approx N/2$0 higher performance over FracDRAM. For cold-boot destruction, the reported speedups are $k \approx N/2$1 over FracDRAM’s neutralize-only approach and $k \approx N/2$2 over RowClone (Yuksel et al., 2023).

The ADRA line of work shows that SiMRA is not limited to symmetric DRAM majority. Conventional multi-wordline CiM maps $k \approx N/2$3 and $k \approx N/2$4 to the same bitline current, so non-commutative functions such as subtraction are ambiguous. ADRA resolves this by driving the two simultaneously activated rows with different read voltages, producing four unique current sums and adding a third sense amplifier to discriminate the middle pair. The sensed outputs are $k \approx N/2$5, $k \approx N/2$6, and $k \approx N/2$7, from which

$k \approx N/2$8

Using a small compute block, ADRA supports $k \approx N/2$9, $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$0, $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$1, subtraction, and comparison in one access. Quantitatively, the work reports a $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$2–$OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$3 decrease in energy-delay product relative to two-access near-memory baselines, with peripheral overheads of $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$4–$OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$5 for full parallelism or $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$6–$OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$7 with column sharing (Malhotra et al., 2022).

4. Entropy generation and SiMRA-based TRNGs

SiMRA also admits an intentionally metastable operating regime in which the SA does not implement a deterministic majority but instead resolves randomly because the aggregate signal falls below the reliable sensing margin. QUAC-TRNG is the first explicit DRAM-based realization of this idea using four-row activation. The implementation uses conflicting row patterns, for example Rows 0 and 2 initialized to all “1” and Rows 1 and 3 initialized to all “0,” so that the total bitline deviation approaches zero. On 136 commodity DDR4 chips from one major manufacturer, QUAC-TRNG reported that certain patterns, such as “0111,” produce on average approximately 11 bits of entropy per 512-bit cache block and up to approximately 53 bits in the best blocks. Entropy varies spatially and with temperature but was reported as stable over weeks (Olgun et al., 2021).

To remove residual bias, QUAC-TRNG collects 256 bits worth of raw entropy from a high-entropy segment and applies SHA-256 to obtain a 256-bit uniformly random output. Under DDR4-2400, the reported throughput per channel is $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$8 Gb/s for a one-bank configuration, $OUT = 1 \iff V_{BL} > V_{DD}/2 \iff N_{1} > M/2,$9 Gb/s with bank-group parallelism (BGP), and $M$0 Gb/s with RowClone plus BGP. The same work reports that this $M$1 Gb/s scales nearly linearly with bus rate and exceeds $M$2 Gb/s on lightly loaded systems. After normalization to a four-channel DDR4-2400 system and fairness via the same SHA-256 post-processing, QUAC-TRNG is reported to outperform D-RaNGe and Talukder+ by $M$3 in the basic comparison and by $M$4 against throughput-enhanced baselines. Its outputs pass all 15 NIST STS tests with $M$5-values uniformly above $M$6 (Olgun et al., 2021).

The 2025 experimental study generalized this to SiMRA-TRNG designs based on 2-, 4-, 8-, 16-, and 32-row activation and characterized 96 SK Hynix DDR4 chips in detail. It reports that entropy generally increases with activation width, that data pattern and temperature significantly affect entropy, and that all five SHA-256-post-processed variants pass every NIST SP 800-22 test on collected 1 Gb bitstreams (Yuksel et al., 23 Oct 2025).

Activated rows	Average cache-block entropy (bits)	Max throughput improvement vs. 4-row QUAC
2	22.87	1.15×
4	25.17	baseline
8	29.47	1.99×
16	34.54	1.82×
32	40.41	1.39×

The same study reports average throughputs of $M$7 Gb/s for 2-row activation, $M$8 Gb/s for 8-row activation, $M$9 Gb/s for 16-row activation, and $V_{GREAD1}$0 Gb/s for 32-row activation. The highest reported throughput gain over prior 4-row QUAC-TRNG is $V_{GREAD1}$1, achieved with 8-row activation. The entropy maximum occurs when the fraction of logic-1 cells is approximately one half: for $V_{GREAD1}$2, the pattern “01” yields $V_{GREAD1}$3 more entropy than “11” or “00”; for $V_{GREAD1}$4, the maximum occurs at 16 or 17 ones. Spatial variation is also strong: for $V_{GREAD1}$5, subarrays in the end third of a bank can exhibit up to $V_{GREAD1}$6 higher average entropy than those in the middle. Temperature degrades the entropy source: for 32-row activation, increasing temperature from $V_{GREAD1}$7C to $V_{GREAD1}$8C decreases average entropy by $V_{GREAD1}$9 (Yuksel et al., 23 Oct 2025).

These TRNG results establish a recurring SiMRA pattern: maximizing randomness requires selecting rows, patterns, and operating conditions that push the SA into metastability rather than away from it. A plausible implication is that SiMRA-based entropy generation is best treated as a characterization-driven operating mode rather than as a fixed property of all simultaneously activated row groups.

5. Device-specific signatures and PUF responses

The same analog mechanism can also produce repeatable signatures rather than random outputs. The 2026 SiMRA-PUF study states this explicitly: some bitlines deterministically resolve the same way every trial, whereas others resolve randomly if the residual perturbation $V_{GREAD2}$0 falls within the SA metastability window. SiMRA-PUF constructs physical unclonable function responses by selecting simultaneously activated row (SAR) groups whose bits flip least across repeated trials, rather than groups with the highest entropy (Baser et al., 13 Jun 2026).

The reported procedure is as follows. Subarray boundaries are first reverse-engineered via RowClone, and candidate SAR groups are then discovered using an APA+WR test. For signature generation, a balanced data pattern is written to each row in the SAR group, an ACT→PRE→ACT sequence with reduced $V_{GREAD2}$1 and $V_{GREAD2}$2 opens $V_{GREAD2}$3 rows concurrently, and one activated row is read with nominal timing to obtain a 64K-bit raw signature. This is repeated 100 times per SAR group and per data pattern; the representative PUF instance is the SAR group whose bits exhibit the least flipping on average (Baser et al., 13 Jun 2026).

Similarity is measured using the Jaccard index

$V_{GREAD2}$4

where $V_{GREAD2}$5 and $V_{GREAD2}$6 are the sets of bit positions reading “1” in two signatures. Intra-device similarity corresponds to average $V_{GREAD2}$7 across trials on the same chip, while inter-device uniqueness corresponds to average $V_{GREAD2}$8 across chips under the same challenge.

Activated rows	Average intra-Jaccard	Average inter-Jaccard
2	89.02%	3.98%
4	89.81%	2.37%
8	93.03%	3.44%
16	94.06%	2.92%
32	94.86%	3.24%

These figures indicate increasing repeatability with larger activation counts, while inter-device overlap remains low. The study compares SiMRA-PUF against a state-of-the-art Frac-based DDR4 PUF reporting intra-Jaccard of approximately $V_{GREAD2}$9. SiMRA-PUF at $V_{BL}=V_{DD}/2 \pm \Delta V$00 is reported to be within $V_{BL}=V_{DD}/2 \pm \Delta V$01 of that figure, while the 2-row design provides the lowest latency. The reported evaluation latencies are $V_{BL}=V_{DD}/2 \pm \Delta V$02 ns for $V_{BL}=V_{DD}/2 \pm \Delta V$03, $V_{BL}=V_{DD}/2 \pm \Delta V$04 ns for $V_{BL}=V_{DD}/2 \pm \Delta V$05, $V_{BL}=V_{DD}/2 \pm \Delta V$06 ns for $V_{BL}=V_{DD}/2 \pm \Delta V$07, $V_{BL}=V_{DD}/2 \pm \Delta V$08 ns for $V_{BL}=V_{DD}/2 \pm \Delta V$09, and $V_{BL}=V_{DD}/2 \pm \Delta V$10 ns for $V_{BL}=V_{DD}/2 \pm \Delta V$11, compared with $V_{BL}=V_{DD}/2 \pm \Delta V$12 ns for Frac-PUF; thus the 2-row SiMRA-PUF is approximately $V_{BL}=V_{DD}/2 \pm \Delta V$13 faster, while the 32-row configuration is approximately $V_{BL}=V_{DD}/2 \pm \Delta V$14 slower (Baser et al., 13 Jun 2026).

Temperature mismatch between enrollment and evaluation reduces similarity: the minimum intra-Jaccard strictly decreases as $V_{BL}=V_{DD}/2 \pm \Delta V$15 grows from $V_{BL}=V_{DD}/2 \pm \Delta V$16C to $V_{BL}=V_{DD}/2 \pm \Delta V$17C. The study notes that 2-row and 32-row designs exhibit the best thermal stability and suggests enrolling golden signatures at multiple temperatures, following prior DRAM-PUF practice. It also reports that 8 Gb M-die and J-die chips show slightly higher inter-Jaccard than 4 Gb A-die chips, suggesting a dependence on density and die revision (Baser et al., 13 Jun 2026).

6. Reliability limits, interference phenomena, and architectural outlook

SiMRA’s analog nature also creates non-ideal interactions beyond the intended operand rows and columns. The most detailed treatment is PuDGhost, which studies corruption of processing-using-DRAM outputs due to two interference sources: data in adjacent non-activated rows and data in concurrently computing columns. On 96 real DDR4 chips, the study reports that adjacent-row data affects SiMRA outputs by up to $V_{BL}=V_{DD}/2 \pm \Delta V$18 for random inputs, while concurrently computing columns affect outputs by up to $V_{BL}=V_{DD}/2 \pm \Delta V$19 for random inputs (Tokuda et al., 17 Jun 2026).

Adjacent-row interference biases the normalized proportion of “1” outputs up or down depending on whether neighboring non-activated rows store mostly ones or zeros. The reported bias grows monotonically with the fraction of logic-1 in adjacent rows, and structured patterns with the same fraction of ones behave similarly. Temperature has negligible impact on this source, within $V_{BL}=V_{DD}/2 \pm \Delta V$20 across $V_{BL}=V_{DD}/2 \pm \Delta V$21–$V_{BL}=V_{DD}/2 \pm \Delta V$22C. Concurrent-column interference is more severe: for 2- and 4-row activation the bias rises monotonically with the fraction of ones in other columns, but for activation widths of 8 or more rows the relation becomes non-monotonic, and the bias can reverse at all-ones settings. The magnitude peaks at up to $V_{BL}=V_{DD}/2 \pm \Delta V$23 error at 16-row activation (Tokuda et al., 17 Jun 2026).

PuDGhost proposes countermeasures at both screening and layout levels. With base screening, the study reports a column break rate of $V_{BL}=V_{DD}/2 \pm \Delta V$24 and BER of $V_{BL}=V_{DD}/2 \pm \Delta V$25. CS-1-01, which screens columns under both all-zero and all-one adjacent-row extremes, reduces the break rate to approximately $V_{BL}=V_{DD}/2 \pm \Delta V$26 and BER to $V_{BL}=V_{DD}/2 \pm \Delta V$27, at $V_{BL}=V_{DD}/2 \pm \Delta V$28 throughput relative to base. CS-2-1, which fixes adjacent rows to all-ones in both screening and execution, yields approximately $V_{BL}=V_{DD}/2 \pm \Delta V$29 break rate, BER of $V_{BL}=V_{DD}/2 \pm \Delta V$30, and $V_{BL}=V_{DD}/2 \pm \Delta V$31 throughput. A dedicated spacer-row layout inserts seven isolation rows per 1024-row subarray, an area overhead of $V_{BL}=V_{DD}/2 \pm \Delta V$32 (Tokuda et al., 17 Jun 2026).

The implications extend beyond deterministic computation. Under hostile row or column interference conditions, the PuDGhost study reports that SiMRA-based TRNG entropy can drop to $V_{BL}=V_{DD}/2 \pm \Delta V$33 and $V_{BL}=V_{DD}/2 \pm \Delta V$34 of baseline, respectively, corresponding to approximately $V_{BL}=V_{DD}/2 \pm \Delta V$35 loss. This indicates that any SiMRA-TRNG design that does not pin non-source data exactly as screened can lose most of its randomness (Tokuda et al., 17 Jun 2026).

Several open architectural questions recur across the literature. QUAC-TRNG notes possible reliability concerns from aggressive timing violations, including accelerated aging and disturbance of neighboring rows, as well as temperature and voltage drift, side-channel and fault attacks, and the possibility of adding a dedicated SiMRA command such as ACT4 in future DRAM standards (Olgun et al., 2021). PULSAR and the 2024 characterization similarly argue for explicit controller and standard support, for example an ACTM command, stable-row allocation mechanisms, and scheduler awareness of row groups, power, and thermal budgets (Yuksel et al., 2023, Yuksel et al., 2024). Taken together, these results suggest that SiMRA is best viewed not as a single primitive but as a controllable analog regime: with appropriate row selection and peripheral handling it can produce deterministic majority, arbitrary CiM, repeatable PUF signatures, or high-entropy random bits, yet the same regime remains sensitive to device variation, layout locality, and non-operand coupling.