Reconfigurable Physical Unclonable Functions

• rPUFs are physical unclonable functions with reconfigurable challenge-response behavior that allow a single device to produce multiple, independent fingerprints.
• They employ diverse reconfiguration methods—ranging from CMOS and FPGA routing to FeFET and photonic state changes—for improved key generation and authentication.
• rPUFs enhance security by refreshing exposed challenge-response pairs, thereby mitigating modeling attacks and supporting applications from IoT to quantum authentication.

Reconfigurable Physical Unclonable Functions (rPUFs) are physically unclonable functions whose challenge–response behavior can be refreshed after fabrication, allowing the same hardware instance to realize a new fingerprint, a new entropy-to-bit mapping, or a new configuration-dependent response family without replacing the device. Across the literature, reconfiguration is realized in several distinct ways: by changing internal circuit topology in CMOS cells, by reprogramming routing or delay composition in FPGA and ring-oscillator fabrics, by invoking stochastic state updates in FeFET and SOT-MRAM devices, and by retuning the transfer matrix or scattering landscape of integrated photonic structures (Li et al., 2021, Spenke et al., 2016, Guo et al., 2022, Wang et al., 22 Aug 2025, Smith et al., 2020, Nocentini et al., 2022, Sarantoglou et al., 14 May 2026). The topic therefore spans weak and strong PUF regimes, analog and digital readout, electronic and photonic substrates, and both classical and quantum authentication settings.

1. Definition and conceptual scope

A recurring definition in the literature is that an rPUF permits the same physical object to produce a new, statistically independent fingerprint on demand. In FeFET work, reconfigurability is defined as the ability to refresh challenge–response pairs to produce a statistically independent fingerprint for the same physical instance, without replacing hardware (Guo et al., 2022). In CMOS static-cell work, the emphasis is different: reconfiguration changes the cell’s internal connectivity to select a more stable entropy mapping, thereby improving reliability while preserving uniqueness and low overhead (Li et al., 2021). In photonic meshes and optical scattering systems, reconfiguration is typically the programming of a new interferometric transfer function or scattering profile, so that the same disorder source underlies many distinct programmed challenge spaces (Jacinto et al., 2020, Nocentini et al., 2022).

This diversity makes one conceptual distinction essential. In some rPUFs, the underlying physical disorder is fixed and only the mapping from disorder to output changes. That is the case for the self-regulated CMOS inverter rPUF, in which threshold-voltage mismatch remains the entropy source while the internal comparison topology is altered (Li et al., 2021), and for programmable photonic meshes, where fabrication-induced phase offsets or coupler imbalance remain fixed while heater settings change the realized unitary or spectrum (Smith et al., 2020, Sarantoglou et al., 14 May 2026). In other rPUFs, reconfiguration explicitly changes device state. FeFET designs repeat reset–write–compare–split cycles to exploit cycle-to-cycle stochasticity (Guo et al., 2022), SOT-MRAM designs apply dual pulses to alter switching outcomes (Wang et al., 22 Aug 2025), and the Hyper PUF optically transforms a polymer–liquid-crystal scattering medium into different reversible levels (Nocentini et al., 2022).

A second distinction concerns function class. Some rPUFs are weak PUFs optimized for key generation and device identification, with few exposed CRPs and strong stability requirements, as in the CMOS subthreshold inverter design (Li et al., 2021). Others are explicitly strong or strong-like, with large programmable CRP spaces, as in interferometer meshes, FeFET challenge arrays, route-based interposer PUFs, and remotely instantiated FPGA arbiters (Smith et al., 2020, Guo et al., 2022, Spenke et al., 2016, Tashdid et al., 16 Jan 2026). A common misconception is therefore that “reconfigurable” denotes a single architectural pattern. The literature instead uses the term for several mechanisms that share only one property: controlled post-fabrication change of the effective PUF mapping.

2. Physical mechanisms and architectural families

Electronic rPUFs span at least four major substrate classes. In 65 nm CMOS, a compact static cell built from a 4-stage subthreshold inverter chain exploits local threshold-voltage mismatch, with the first stage biased at a high-gain switching point and later stages resolving the mismatch to a rail-level output. Reconfiguration is performed by merging the first two inverters into a single larger stage through an NMOS “reconfigure” transistor, yielding two configurations per cell with zero area overhead (Li et al., 2021). In configurable ring-oscillator PUFs, LUT-based interstage crossing structures permute inverter-stage connections; a configuration vector $\boldsymbol{\kappa} = (S_1, S_2, \ldots, S_{m-1})$ reshapes delay paths, while the challenge selects oscillator pairs or paths for comparison (Zhang et al., 2018). In remotely reconfigured FPGA arbiters, the PUF does not exist until a verifier programs a random bitstream that places and routes delay stages across a reserved region of the FPGA fabric (Spenke et al., 2016). In InterPUF, the physical substrate is the reconfigurable interposer itself: route-based differential delay races are instantiated over mesh routing resources and protected by MPC so that raw signatures never leave the interposer (Tashdid et al., 16 Jan 2026).

Stateful memory-like rPUFs use a different mechanism. The FeFET strong PUF exploits cycle-to-cycle stochastic polarization switching in HfO$_2$-based ferroelectric devices. Each cell contains two FeFETs and a coupling capacitor; repeated reset and weak-write operations on one FeFET produce different polarization configurations and hence different $V_{\mathrm{th}}$ and $V_x$, after which a strong split operation stabilizes the cell into a binary state (Guo et al., 2022). The SOT-MRAM rPUF instead controls switching probability with two oppositely polarized write pulses. Under an independent-events model, the final write-success rate is

$$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$

and a pulse-amplitude offset $\beta$ is used to widen the operating window and reduce temperature sensitivity (Wang et al., 22 Aug 2025).

Photonic rPUFs are at least as diverse as electronic ones. A large silicon-on-insulator quantum photonics processor uses 88 two-by-two MZIs arranged in a triangular nearest-neighbor mesh; reconfiguration is achieved by changing internal heater-controlled phases, thereby changing the network transfer matrix and response histograms (Smith et al., 2020). A closely related proposal uses the same class of mesh as a fully optical authentication primitive for both classical and quantum protocols, treating different phase vectors as many seemingly independent PUF instances (Jacinto et al., 2020). Other photonic designs shift from linear mesh transfer to device-specific nonlinear filters. The RN-ELM/rPUF uses random nonlinearities from fabrication-induced imperfections in microring resonators embedded in a reconfigurable photonic integrated chip, with device-specific frequency-to-power responses acting as entropy sources (Sarantoglou et al., 18 Dec 2025). A SmartLight hexagonal mesh similarly maps device-specific passive phase offsets $\phi_0$ and programmable phase settings $\Delta\phi$ into unique equalizer weights, so the same hardware acts simultaneously as a neuromorphic accelerator and a PUF (Sarantoglou et al., 16 May 2025). Low-symmetry photonic quasicrystal interferometers introduce a different regime: distributed multiple scattering in moiré quasicrystal waveguides creates aperiodic spectra, and thermo-optic control of the two arms drives distinct, low-mutual-information profiles (Tarik et al., 9 Jul 2025). The Hyper PUF uses a disordered polymer-dispersed and polymer-stabilized liquid-crystal film, where a blue “transformer challenge” optically switches internal scattering structure while a red coherent probe reads out speckle responses (Nocentini et al., 2022). Finally, a SiN 6-by-6 programmable unitary mesh uses a fixed fingerprint $\phi_{\mathrm{off}}$ of passive phase offsets and programmable heater voltages $V$ to realize a quantum-secure rPUF whose readout can be refreshed by reprogramming the realized unitary $_2$0 (Sarantoglou et al., 14 May 2026).

3. Reconfiguration operations, enrollment, and response extraction

Enrollment procedures in rPUFs are tightly coupled to the reconfiguration mechanism. In the self-regulated CMOS rPUF, instability is identified by sweeping body bias rather than temperature during enrollment. The threshold relation

$_2$1

is used to justify body-bias sweeping as an emulator of temperature-induced threshold shifts. The workflow is explicit: measure a golden key by majority vote at nominal conditions; sweep $_2$2; mark any flipping bit unstable; assert the per-column reconfiguration control for marked cells; then re-enroll the golden key. The reconfiguration map is stored off-chip, and no on-chip redundancy or ECC is required (Li et al., 2021).

In configurable RO key-sharing systems, enrollment is delegated to a Trusted Third Party. The TTP enumerates path configurations, reads counter “Counts,” trains a delay matrix $_2$3 with machine learning, determines a reliability threshold $_2$4, and synthesizes device-specific challenge/configuration tuples that force multiple devices to output the same target key. The path measurement model is written as

$_2$5

with $_2$6 the binary path-selection matrix. This procedure is explicitly intended to support key sharing without transmitting the key itself (Zhang et al., 2018). In remotely reconfigured FPGA arbiters, enrollment consists of choosing a second challenge in the form of an FPGA configuration, selecting metastable m-challenges on a reference device, and storing the resulting 100-bit template fingerprint for later verification (Spenke et al., 2016).

FeFET and SOT-MRAM rPUFs rely on write-driven re-enrollment. The FeFET sequence is reset, weak write, measure $_2$7, reset again, repeat the weak write, compare the two $_2$8 values, and then strongly split the cell into a stable state. At the array level, the challenge-dependent intermediate node obeys

$_2$9

with

$V_{\mathrm{th}}$0

and the response is determined by whether $V_{\mathrm{th}}$1 exceeds $V_{\mathrm{th}}$2 (Guo et al., 2022). In SOT-MRAM, the reconfiguration primitive is the dual pulse itself, optionally combined with TMV, SWB, and XOR post-processing; the paper emphasizes that the operating point can be chosen once for industrial temperature range operation without dynamic temperature feedback (Wang et al., 22 Aug 2025).

Photonic rPUFs use optical or electro-thermal control as the reconfiguration interface. In the 88-MZI interferometer network, a challenge is the vector of heater voltages applied to the internal phase shifters, and the response is the normalized distribution of output intensities on $V_{\mathrm{th}}$3 output ports. The output field is modeled as

$V_{\mathrm{th}}$4

with measured intensities $V_{\mathrm{th}}$5 (Smith et al., 2020). In the SmartLight mesh and RN-ELM photonic systems, heater phases, active filter selection, coupling conditions, FM scaling, and quantization precision are all potential configuration knobs, and responses are extracted downstream from digitized detector outputs, often after projection, Gray encoding, and random bit selection (Sarantoglou et al., 16 May 2025, Sarantoglou et al., 18 Dec 2025). In the Hyper PUF, the challenge is explicitly two-part, $V_{\mathrm{th}}$6, and the response is a binarized speckle key after Gabor filtering (Nocentini et al., 2022). In the quantum-secure SiN mesh, enrollment requires the verifier to characterize the passive phase-offset vector, reconstruct $V_{\mathrm{th}}$7 and its inverse, and then authenticate by single-photon challenge states while refreshing $V_{\mathrm{th}}$8 between sessions if desired (Sarantoglou et al., 14 May 2026). InterPUF adds a cryptographic wrapper: stable route bits are majority-voted, hashed into $V_{\mathrm{th}}$9, and then used only inside Yao 2PC during runtime authentication (Tashdid et al., 16 Jan 2026).

4. Reliability, uniqueness, randomness, and CRP capacity

Reported performance spans several orders of magnitude, reflecting major substrate differences. In the 65 nm CMOS static rPUF, raw native BER at nominal conditions is $V_x$0, falling to $V_x$1 after reconfiguration; the design shows $V_x$2 temperature coefficient and $V_x$3 voltage coefficient over $V_x$4 to $V_x$5 and $V_x$6 to $V_x$7, with mean inter-die HD $V_x$8, intra-die mean HD $V_x$9 after stabilization, and total energy $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$0 in LP mode (Li et al., 2021). The FeFET strong rPUF reports Hamming Weight $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$1, mean inter-chip HD $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$2 with $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$3, BER $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$4, reconfiguration HD $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$5 with $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$6, and energy $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$7 (Guo et al., 2022). The SOT-MRAM rPUF reports 7-bit XOR uniformity with fitted $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$8 and $$F = \mathrm{WSR1} - \mathrm{WSR1}\times \mathrm{WSR2},$$9, BER $\beta$0 with SWB at nominal conditions, and dual-pulse plus XOR inter-reconfiguration HD $\beta$1 (Wang et al., 22 Aug 2025).

CRP capacity is especially prominent in photonic and programmable-routing designs. The 66-MZI integrated optical interferometer network derives an architecture-feasible CRP count of

$\beta$2

for a single 66-MZI light cone with 10-bit quantization, and approximately $\beta$3 total distinct CRPs across three such subsets on the full device (Smith et al., 2020). The fully optical authentication paper cites the same full-device figure and interprets it as enough to imitate a large array of single-response PUFs (Jacinto et al., 2020). In CRO PUFs, the configuration space scales as $\beta$4 with $\beta$5 pair selections, and a 4-by-5 CRO PUF is stated to generate 10,368 CRPs (Zhang et al., 2018). InterPUF instead reports practical digest sizes of 256 or 512 bits after stability filtering, with route-pair populations generated from mesh paths and permutations rather than a monolithic arbiter chain (Tashdid et al., 16 Jan 2026).

Randomness and authentication figures also differ by readout model. The CMOS static rPUF passes NIST SP 800-22 and SP 800-90B tests on 40,960 bits across 10 chips (Li et al., 2021). The SOT-MRAM design passes NIST SP 800-22 with representative p-values such as Frequency $\beta$6, BlockFrequency $\beta$7, and Runs $\beta$8 (Wang et al., 22 Aug 2025). The SmartLight photonic mesh, using equalizer-weight extraction, reports $\beta$9 for three nodes, 3-bit precision, and phase threshold $\phi_0$0, together with false positive/negative probability $\phi_0$1 at the abstract level (Sarantoglou et al., 16 May 2025). The RN-ELM photonic rPUF reports inter-distribution mean NHD $\phi_0$2, intra-distribution mean NHD $\phi_0$3, $\phi_0$4 for $\phi_0$5, $\phi_0$6, $\phi_0$7, and $\phi_0$8 for $\phi_0$9, $\Delta\phi$0 (Sarantoglou et al., 18 Dec 2025). The SiN quantum-secure photonic rPUF reports classical inter-FHD mean $\Delta\phi$1 and intra-FHD mean $\Delta\phi$2, while Monte Carlo analysis of the quantum readout yields equal error rates as low as $\Delta\phi$3 (Sarantoglou et al., 14 May 2026).

A useful common metric remains Hamming distance,

$\Delta\phi$4

and BER is often written as the number of bit flips divided by the number of evaluated bits (Li et al., 2021). Yet the literature also shows that HD alone is not sufficient. Some photonic works report strong uniqueness but explicitly do not report min-entropy, bias analysis, or extractor parameters (Smith et al., 2020). This suggests that raw uniqueness, even when near ideal, should not be conflated with turnkey key-extraction readiness.

5. Security properties, misconceptions, and unresolved tensions

The principal security motivation for reconfiguration is CRP hygiene. When a device can rotate its internal mapping, previously observed CRPs become less useful, and adversaries must restart learning or measurement after each refresh. This is explicit in the FeFET literature, where low-cost reconfiguration is proposed as a way to limit the number of CRPs exposed before refreshing (Guo et al., 2022), and in the FPGA literature, where the verifier remotely instantiates a new arbiter layout just before authentication so that the PUF “simply does not exist” beforehand (Spenke et al., 2016). InterPUF extends the same logic to chiplet systems: route remapping enlarges the challenge space, retires suspect subsets, and hashes stable route bits before any MPC-secured verification, so raw CRPs never leave the interposer (Tashdid et al., 16 Jan 2026).

At the same time, the literature repeatedly rejects a stronger claim sometimes attached to rPUFs, namely that reconfiguration alone makes a design immune to modeling or side-channel attacks. Several photonic papers state the caveat directly. The integrated optical interferometer network is linear and, with sufficient CRPs and calibration, an adversary could estimate the transfer matrix; the authors therefore recommend operating such devices in “uncalibrated” mode for stronger PUF behavior and pursuing more complex interconnections or feedback loops (Smith et al., 2020). The quantum/classical MZI authentication paper similarly grounds security in both device complexity and protocol structure, not in reconfiguration by itself (Jacinto et al., 2020). In electronic systems, CRO PUF key sharing relies on a TTP that protects pre-trained device models (Zhang et al., 2018), and FPGA arbiter security depends on authenticated bitstream delivery and replay protection (Spenke et al., 2016).

Another recurring issue is the control plane as an attack surface. In the CMOS static rPUF, body-bias and reconfiguration-control lines must be access-controlled; the paper explicitly recommends gating RC and body bias under secure firmware, authenticating reconfiguration-map updates, and monitoring tamper events (Li et al., 2021). In photonic systems, coupling drift, heater drift, and temperature sensitivity are acknowledged as practical side channels or reliability hazards (Smith et al., 2020, Sarantoglou et al., 18 Dec 2025). In the Hyper PUF, leakage of the transformer challenge $\Delta\phi$5 would reveal which internal level is active, so concealment or authenticated control of the blue write path is a stated requirement (Nocentini et al., 2022). In SiN quantum-secure meshes, the security model assumes the maximally mixed challenge ensemble conceals the underlying unitary from passive observers, but active bright-light or coherent-state probing is discussed as a deployment concern requiring watchdog detectors, filtering, and isolation (Sarantoglou et al., 14 May 2026).

A final misconception concerns “raw” operation. Several of the best reported metrics depend on stabilization, majority voting, SWB, XOR, or projection-based extraction rather than direct one-shot raw responses. The CMOS design uses TMV-11 after reconfiguration for residual noise (Li et al., 2021). The SOT-MRAM design combines dual pulses with SWB, TMV, and XOR (Wang et al., 22 Aug 2025). The SmartLight and RN-ELM photonic designs derive keys from projected and quantized equalizer weights rather than directly thresholding analog spectra (Sarantoglou et al., 16 May 2025, Sarantoglou et al., 18 Dec 2025). This does not diminish their relevance, but it does mean that any comparison between rPUFs must separate raw physical stability, enrollment-time filtering, and post-processing overhead.

6. Applications and research directions

The most established application class is secure key generation and device authentication. The self-regulated CMOS rPUF is positioned for reliable key derivation in resource-constrained IoT and embedded systems, with near-ideal uniqueness and very low BER after reconfiguration (Li et al., 2021). CRO PUFs extend this to one-to-one key sharing, where different devices reconstruct the same shared key from device-specific configurations without transmitting the key across the network (Zhang et al., 2018). FeFET and SOT-MRAM designs target low-power IoT endpoints, emphasizing low energy, robustness, and rapid or repeated reconfiguration for lifecycle key rotation (Guo et al., 2022, Wang et al., 22 Aug 2025).

A second application class is programmable authentication in reconfigurable computing and packaging. The FPGA arbiter approach treats remote reconfiguration as security-by-unavailability for chip biometrics (Spenke et al., 2016). InterPUF generalizes the idea to chiplet ecosystems: the reconfigurable interposer becomes a distributed root of trust, and authentication is performed collaboratively through MPC rather than by exposing raw PUF responses or relying on a centralized anchor (Tashdid et al., 16 Jan 2026). This suggests a broader role for rPUFs in post-fabrication programmable systems, where the same routing flexibility that enlarges the attack surface can also enlarge the physical challenge space.

Photonic rPUFs add two further directions. One is high-capacity optical authentication and anti-counterfeiting. Integrated interferometer meshes offer very large CRP spaces (Smith et al., 2020), Hyper PUFs provide multiple co-existing levels within one token (Nocentini et al., 2022), and low-symmetry quasicrystal interferometers provide erasable mutual information and revocable spectral keys with approximately $\Delta\phi$6 unique keys under dual-input modulation (Tarik et al., 9 Jul 2025). The other is multifunctionality. The SmartLight and RN-ELM works show that a reconfigurable photonic chip can act simultaneously as an inference engine and a PUF, with device-specific equalizer weights or nonlinear filter responses serving both computing and authentication roles (Sarantoglou et al., 16 May 2025, Sarantoglou et al., 18 Dec 2025). The literature presents this not as a rhetorical analogy but as a concrete dual-use architecture.

Quantum authentication is an especially active frontier. Fully optical MZI meshes have been proposed as classical and quantum authenticators whose large configuration space imitates many single-response PUFs (Jacinto et al., 2020). The SiN quantum-secure photonic rPUF goes further by combining reconfigurable unitary control with single-photon readout, maximally mixed channel ensembles, and session-by-session phase refresh, reporting equal error rates down to $\Delta\phi$7 in numerical evaluation (Sarantoglou et al., 14 May 2026). This suggests that reconfigurability may be particularly valuable when the authentication protocol itself is adaptive, session-bound, or quantum-limited.

Several open problems recur across the field. Long-term field aging and retention remain open in CMOS, FeFET, and magnetic devices (Li et al., 2021, Guo et al., 2022, Wang et al., 22 Aug 2025). Entropy characterization and extractor design remain incomplete in some high-capacity photonic systems (Smith et al., 2020). Packaging stability, coupling drift, and temperature compensation are central challenges for practical photonic deployment (Smith et al., 2020, Sarantoglou et al., 14 May 2026). Formal modeling-resistance evaluations beyond baseline ML attacks are still limited for several new rPUF families, including low-symmetry photonic quasicrystals and some multifunctional photonic meshes (Tarik et al., 9 Jul 2025, Sarantoglou et al., 16 May 2025). A plausible implication is that future rPUF research will be judged less by reconfiguration alone than by how tightly it integrates reconfiguration with enrollment methodology, environmental stabilization, cryptographic binding, and attack-surface control.