SiMRA-PUF: DRAM-Based PUF via Row Activation

• SiMRA-PUF is a DRAM-based physically unclonable function that employs simultaneous multi-row activation under reduced timing constraints to generate stable, device-specific signatures.
• The approach harnesses charge-sharing and sensing in commercial DDR4 DRAM, achieving high intra-device repeatability and low inter-device similarity by exploiting inherent process variations.
• Extensive experiments on SK hynix DDR4 chips reveal a tradeoff between activation row count and evaluation latency, optimizing runtime authentication performance.

Searching arXiv for papers on SiMRA-PUF and closely related DRAM/PUF work. SiMRA-PUF is a DRAM-based physically unclonable function that uses simultaneous multiple-row activation (SiMRA) in commercial off-the-shelf DDR4 DRAM to generate device-specific signatures from charge-sharing and sensing outcomes that depend on process and design variation (Baser et al., 13 Jun 2026). In this construction, a challenge selects a DRAM location at the granularity of a bank and subarray, multiple rows in the same subarray are activated with reduced timing constraints, and the resulting sensed bit pattern serves as the PUF response. The reported objective is to obtain responses that are repeatable within a device, different across devices, and fast enough for runtime evaluation, making the mechanism suitable for authentication and related hardware-rooted security functions (Yuksel et al., 18 Jun 2026).

1. Definition, scope, and terminology

SiMRA-PUF was introduced as the first DRAM-based PUF that uses SiMRA-generated signatures as PUF responses in commercial DDR4 chips (Baser et al., 13 Jun 2026). The underlying primitive is simultaneous multiple-row activation, realized by an ACT $\rightarrow$ PRE $\rightarrow$ ACT sequence, abbreviated APA, while violating DRAM timing constraints $t_{RAS}$ and $t_{RP}$. The challenge is defined as a $(Bank_{ID}, Subarray_{ID})$ pair, together with the selected data pattern, and the response is the bit signature produced after simultaneous activation of the chosen row group (Baser et al., 13 Jun 2026).

Within the broader PUF literature represented here, the term “SiMRA-PUF” is specific to the DRAM construction based on simultaneous multiple-row activation (Baser et al., 13 Jun 2026). Conceptually related but differently named designs include the recurrent current-mirror-array RNN-PUF (Shah et al., 2018) and the adaptive multi-bit SRAM topology based analog PUF built around a Current Mirror Array and configurable ADC (Sharma et al., 2019). In contrast, SRAM-PUF work on start-up-state reliability focuses on cell selection, mismatch metrics, separatrix analysis, and reduction of ECC or fuzzy-extractor overhead rather than simultaneous row activation in DRAM (Alheyasat et al., 2024).

2. Physical mechanism and response formation

The core mechanism exploits what happens when several DRAM rows in the same subarray are activated simultaneously under reduced timings. If those rows are initialized with a balanced data pattern containing opposing values, then the cells share charge with the bitlines, the bitline voltage is perturbed close to the reference $V_{DD}/2$, and small process and design variations perturb the final bitline voltage enough that sense amplifiers resolve each bitline to $0$ or $1$ in a device-specific way (Baser et al., 13 Jun 2026). The signature is therefore rooted in manufacturing variation in DRAM capacitors, access transistors, sense amplifiers, and surrounding circuitry (Yuksel et al., 18 Jun 2026).

The response-generation flow is explicit. For a given challenge, the controller selects the corresponding simultaneously activated row (SAR) group, initializes it with a balanced data pattern, issues the reduced-timing APA sequence, and reads the sense-amplifier outputs as the signature (Yuksel et al., 18 Jun 2026). The authors further constrain usable responses by selecting a SAR group whose 64K-bit response contains at least 512 zeros and 512 ones, computing per-bit Shannon entropy over 100 trials, and then choosing the SAR group with the lowest average per-bit entropy as the representative for that subarray (Baser et al., 13 Jun 2026). The resulting emphasis is on the repeatable subset of the analog behavior: stable outputs define the PUF signature, whereas unstable outputs are not the target resource of the mechanism (Yuksel et al., 18 Jun 2026).

This distinguishes SiMRA-PUF from designs that seek randomness rather than reproducibility. The same simultaneous-multiple-row-activation primitive can be used as a TRNG substrate, but SiMRA-PUF deliberately selects the stable portion of the phenomenon for device identification rather than entropy harvesting (Yuksel et al., 18 Jun 2026). A plausible implication is that the quality of a SiMRA-PUF instance depends not only on the DRAM chip but also on the challenge and data-pattern selection policy used to expose stable threshold-proximal sensing behavior.

3. Characterization methodology and experimental platform

The reported characterization spans 112 DDR4 DRAM chips from 10 modules for the PUF evaluation, with all analyzed chips being SK hynix because SiMRA succeeded on those chips but not on the tested chips from other manufacturers (Baser et al., 13 Jun 2026). The broader experimental campaign covered 144 DDR4 chips from 14 modules across manufacturers, but the PUF analysis concentrates on the 112 SK hynix chips (Baser et al., 13 Jun 2026). The tested devices cover 4 Gb and 8 Gb densities and die revisions A, J, M.

The infrastructure is based on DRAM Bender, an FPGA-based DDR4 characterization platform built on SoftMC-style control, using a host machine, a Xilinx Alveo U200 FPGA board, a DDR4 DIMM with heater pads, and a temperature controller for stable thermal conditions (Baser et al., 13 Jun 2026). This enables precise command sequencing, timing reduction, and controlled thermal testing. To identify rows in the same subarray, the study uses a RowClone-based reverse-engineering method: two rows are in the same subarray if RowClone can copy data between them (Baser et al., 13 Jun 2026). To identify SAR groups, the procedure issues an APA sequence with reduced timings, follows it with a WR command containing a known data pattern, reads back all rows using nominal timings, and treats the rows that contain the written pattern as the simultaneously activated set (Baser et al., 13 Jun 2026).

For each SAR group, the characterization procedure initializes the rows with a balanced data pattern, issues the APA command sequence, reads the signature, and repeats the experiment 100 times to measure stability (Baser et al., 13 Jun 2026). Sampling is extensive: for each module and each activation count, the study samples 10 SAR groups from each of 30 subarrays in 5 randomly selected banks, and in total evaluates 278 data patterns (Baser et al., 13 Jun 2026). The authors also avoid using multiple SAR groups from the same subarray because of observed correlation, which constrains the independence assumptions one might otherwise make when composing responses across groups (Baser et al., 13 Jun 2026).

4. Metrics, quantitative behavior, and latency

SiMRA-PUF is evaluated primarily with the Jaccard index,

$J(A,B)=\frac{|A\cap B|}{|A\cup B|},$

using intra-Jaccard similarity for repeatability and inter-Jaccard similarity for uniqueness (Baser et al., 13 Jun 2026). Higher intra-Jaccard is better, lower inter-Jaccard is better.

Activated rows	Avg. intra-Jaccard	Avg. inter-Jaccard
2	89.02	3.98
4	89.81	2.37
8	93.03	3.44
16	94.06	2.92
32	94.86	3.24

These values show that responses are highly repeatable within a device and highly distinguishable across devices for all tested activation counts (Baser et al., 13 Jun 2026). The general trend is that intra-Jaccard improves as the number of simultaneously activated rows increases, while inter-Jaccard remains low but not strictly monotonic (Baser et al., 13 Jun 2026). The broader memory-centric-computing survey characterizes this construction as the state-of-the-art DRAM-based physical unclonable function and reports the same intra- and inter-Jaccard ranges as evidence of stable and unique signatures (Yuksel et al., 18 Jun 2026).

Latency is a second major metric because the method is intended to be runtime-accessible rather than restricted to slow offline measurement.

PUF design	Evaluation latency
Frac-based PUF	895 ns
SiMRA-PUF (2-row)	843.5 ns
SiMRA-PUF (4-row)	1016.5 ns
SiMRA-PUF (8-row)	1362.5 ns
SiMRA-PUF (16-row)	2054.5 ns
SiMRA-PUF (32-row)	3438.5 ns

The principal comparison is that 2-row SiMRA-PUF has 5.75% lower evaluation latency than the prior state-of-the-art Frac-based PUF (Baser et al., 13 Jun 2026). At larger row counts, latency rises sharply; the memory-centric survey notes that 32-row activation has latency 3.84× that of Frac-based PUF (Yuksel et al., 18 Jun 2026). This yields a direct tradeoff: higher row counts improve average repeatability, but the 2-row version is the fastest and is the only configuration that improves on Frac-based latency (Baser et al., 13 Jun 2026).

5. Temperature sensitivity, density, and die revision

Temperature affects similarity in a manner consistent with other volatile-memory PUFs. The SiMRA-PUF study uses a $50^\circ\text{C}$ enrollment baseline and evaluates responses at $\rightarrow$0, $\rightarrow$1, $\rightarrow$2, and $\rightarrow$3 (Baser et al., 13 Jun 2026). The reported finding is that the minimum intra-Jaccard index for each design strictly decreases as the temperature gap from enrollment grows, indicating reduced repeatability under thermal drift (Baser et al., 13 Jun 2026). The authors therefore suggest enrolling multiple golden responses across temperature intervals to improve deployment robustness (Baser et al., 13 Jun 2026).

The effect of row count on thermal robustness is not monotonic. The paper reports that 2-row activation is most temperature-stable on average, achieving the highest minimum intra-Jaccard at each tested temperature, while 2-row and 32-row activation show the smallest intra-Jaccard drop across the tested range (Baser et al., 13 Jun 2026). This rules out a simple “more rows is always more robust” interpretation.

Architecture matters primarily for uniqueness rather than stability. For 2-row activation, the study finds that DRAM architecture significantly affects uniqueness, and some 8 Gb M-die and 8 Gb J-die modules exhibit higher inter-Jaccard, meaning less unique responses, while response stability remains consistently high across architectures (Baser et al., 13 Jun 2026). A plausible implication is that deployment-oriented evaluation of SiMRA-PUF should treat density and die revision as first-order selection variables, especially when inter-device separability is the dominant requirement.

6. Relation to prior PUF classes and to SRAM-PUF practice

SiMRA-PUF occupies a specific position in the DRAM-PUF design space. Earlier DRAM PUFs exploited startup values, retention failures, access latency variation, read disturbance, and related timing-sensitive effects, but these approaches have practical limitations: startup-value PUFs require a power cycle for every authentication, retention-failure PUFs are slow, and some latency-based proposals require additional circuitry or are less practical (Yuksel et al., 18 Jun 2026). The immediate predecessor identified in the SiMRA-PUF papers is the Frac-based PUF, which repeatedly applies reduced-timing ACT→PRE operations to drive cells toward $\rightarrow$4 before sensing the final resolution (Baser et al., 13 Jun 2026). SiMRA-PUF replaces that fractional-voltage shaping sequence with simultaneous multiple-row activation and achieves lower latency in the 2-row configuration (Yuksel et al., 18 Jun 2026).

Its position also contrasts with SRAM-PUF research. SRAM-PUFs derive signatures from preferred cell start-up states, but repeatability is degraded by noise, temperature, and environmental changes, leading many schemes to rely on ECC or fuzzy extractors for key regeneration (Alheyasat et al., 2024). A recent SRAM design-time study proposes two predictors—$\rightarrow$5 and SID—to estimate what fraction of cells will power up repeatably to the same initial state, with the aim of selecting reliable bits and reducing ECC or fuzzy-extractor dependence (Alheyasat et al., 2024). Separate embedded-system measurements show that even closely related microcontrollers can differ substantially in SRAM-PUF reliability under temperature variation, with fuzzy-extractor tolerance requirements becoming burdensome as noise rises (Zeinzinger et al., 16 Mar 2026). In that context, SiMRA-PUF is notable because the provided text does not describe helper-data mechanisms or explicit ECC for its DRAM responses; the evaluation instead emphasizes intrinsic repeatability and uniqueness of the raw selected signatures (Yuksel et al., 18 Jun 2026).

This suggests a broader methodological distinction. SRAM-PUF practice often starts from noisy start-up bits and then suppresses or corrects instability, whereas SiMRA-PUF constructs its responses from a timing-induced analog sensing regime chosen specifically to expose a stable, device-specific signature in commodity DRAM (Alheyasat et al., 2024). The shared premise across both families is that useful hardware identity is produced by fixed fabrication variation, but the physical operating points, evaluation metrics, and engineering tradeoffs differ substantially.