Stanford Memristor Model in Arbiter PUFs

• Stanford Memristor Model is a filamentary oxide RRAM model that uses coupled variables for tunneling gap and filament radius to capture non-linear switching behavior.
• It employs a current law combining metallic conduction and tunneling-based hopping to model stochastic dynamics critical for delay-based security.
• Integration into Arbiter PUF architectures demonstrates enhanced reliability via Monte Carlo simulations, though achieving optimal uniqueness remains challenging.

Searching arXiv for the specified paper and closely related Stanford memristor model context. The Stanford memristor model, as used in "Arbiter PUF: Uniqueness and Reliability Analysis Using Hybrid CMOS-Stanford Memristor Model" (Rahman et al., 6 Jul 2025), is a filamentary oxide RRAM model in which device behavior is governed by two coupled internal state variables: the tunneling gap width $g(t)$ and the metallic filament radius $r(t)$. In the cited work, the model is employed to represent random filament evolution inside memristive delay elements of an Arbiter PUF implemented with 45nm CMOS technology, with the aim of exploiting stochastic switching behavior for hardware security. Within that usage, the model is characterized by coupled stochastic state equations, a current law that combines metallic and hopping contributions, and parameter choices matched to a 10 nm TiN/HfOₓ/TiOₓ/Pt RRAM device (Rahman et al., 6 Jul 2025).

1. Physical basis and state representation

In the formulation summarized in the PUF study, the Stanford model treats a filamentary oxide RRAM cell as two coupled state variables: $g(t)$, the width of the tunneling gap separating the conductive filament from the electrode, and $r(t)$, the radius of the metallic filament. This representation makes the model explicitly geometric at the state level: one variable captures filament rupture or gap opening, while the other captures filament cross-section (Rahman et al., 6 Jul 2025).

The paper gives the integral form

$$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$

In full differential form,

$$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$

Here, $\frac{dg}{dt}$ and $\frac{dr}{dt}$ are deterministic drift rates, $\chi(t)$ is a zero-mean, unit-RMS white-Gaussian sequence, and $\delta g$ and $r(t)$0 are empirical noise amplitudes associated with gap and radius fluctuations. The functions $r(t)$1 and $r(t)$2 are stated to derive from field-driven oxygen-vacancy generation and recombination kinetics.

The summary further notes that, in the original Stanford SPICE model, these drift terms take Arrhenius-like forms,

$r(t)$3

although the PUF paper does not reproduce these closed forms in detail. This suggests that the model is intended to preserve voltage- and temperature-dependent filament kinetics rather than reduce switching to a purely phenomenological resistance update rule.

2. Current law and resistance interpretation

The net current is modeled as the sum of a metallic channel contribution and a hopping contribution across the gap. The paper states

$r(t)$4

For example, in Li et al., the current components are written as

$r(t)$5

where $r(t)$6 is the device thickness and $r(t)$7 is the tunneling cross-section, often $r(t)$8.

This decomposition is central to the model’s use in delay-based security circuits. The metallic term scales with filament cross-section through $r(t)$9, whereas the hopping term depends exponentially on the gap $g(t)$0. A plausible implication is that modest stochastic perturbations in $g(t)$1 can strongly perturb conduction, and therefore delay, even when the qualitative switching state remains unchanged.

The paper contrasts this with a simpler linear drift description,

$g(t)$2

where $g(t)$3 and $g(t)$4 are the low-resistance and high-resistance limits. In the Stanford model, by contrast, the instantaneous resistance is described as a nonlinear function of $g(t)$5. That distinction is important in the PUF setting because the stochasticity acts directly on physically interpretable state variables rather than only on a scalar resistance interpolation.

3. Parameters and stochastic terms

The paper defines the principal parameters in explicitly physical terms. $g(t)$6 is the total oxide thickness, given as the device height, for example 10 nm. $g(t)$7 is the ionic mobility of oxygen vacancies. $g(t)$8 and $g(t)$9 are the deterministic drift rates for gap and radius evolution and depend on activation energies, enhancement factors, and field bias. $r(t)$0 and $r(t)$1 are the RMS amplitudes of gap and radius fluctuations, and $r(t)$2 is white Gaussian noise $r(t)$3. SET and RESET threshold voltages are described as implicit in the drift-rate functions, which turn on above a certain $r(t)$4 (Rahman et al., 6 Jul 2025).

The oxygen-vacancy parameters reported from Table III in the PUF paper are as follows:

Parameter	Meaning	Value
Adjacent O-vacancy distance	Oxygen-vacancy spacing	0.25 nm
$r(t)$5	O-atom vibration frequency	$r(t)$6 Hz
$r(t)$7	Activation energy for O-vacancy recombination	0.7 eV
$r(t)$8	Field-enhancement factor	0.75 nm
$r(t)$9	Initial gap length	3 nm
$$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$0	Initial filament radius	0.5 nm
$$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$1	Gap distance amplitude	$$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$2 nm

The stochastic terms are added directly to the drift equations. The paper states that the zero-mean Gaussian sequence $$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$3 captures cycle-to-cycle and device-to-device randomness in filament formation and rupture, and that the empirical amplitudes $$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$4 and $$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$5 are tuned to match measured LRS/HRS spread. In this usage, stochasticity is therefore not an auxiliary post-processing assumption; it is embedded in the device dynamics.

4. Use in the Arbiter-PUF architecture

The study integrates the Stanford model into an Arbiter PUF whose circuit topology consists of two parallel delay lines, with each stage implemented as a memristor in parallel with an NMOS switch and controlled by a challenge bit (Rahman et al., 6 Jul 2025). Figure 1 is identified as the single-response PUF and Figure 2 as the multi-response PUF, both followed by an arbiter realized by a D-flip-flop or an RS-latch.

Operation is divided into distinct phases. During a global RESET pulse, each memristor’s $$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$6 state drifts stochastically to a random LRS or HRS, and this seeding establishes a unique pattern of stage delays per chip. In the challenge phase, further small drift imposes challenge-dependent slight shifts in filament geometry and therefore in resistance. In the evaluation phase, identified as $$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$7, a voltage edge propagates down the two paths, and the relative delay is determined by the branch currents associated with hopping and metallic transport.

The paper gives the analytical response rule as

$$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$8

with

$$g(t)\;=\;\int_0^t\!\Bigl(\frac{dg}{dt'}+\delta g\;\chi(t')\Bigr)\,dt' \quad,\quad r(t)\;=\;\int_0^t\!\Bigl(\frac{dr}{dt'}+\delta r\;\chi(t')\Bigr)\,dt' .$$9

Here, $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$0 denotes the resistance difference of the $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$1th memristor pair in the upper and lower arms. Because $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$2 depends on the stochastic state variables $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$3, the inter-chip Hamming distance and intra-chip stability are described as being directly controlled by the Stanford model’s noise terms. This formulation links the compact device model to a standard delay-race PUF abstraction without removing the stochastic filament physics.

5. Simulation methodology and measured criteria

The evaluation reported in the paper uses Monte Carlo analysis to estimate uniqueness and reliability. Intra- and inter-Hamming distances are the stated metrics, and the simulations include both CMOS mismatch and memristor stochasticity. The setup is summarized as follows (Rahman et al., 6 Jul 2025):

Simulation aspect	Reported setup
Temperature	27 °C for both CMOS and memristor
Supply voltage	5 V
CMOS technology	GPDK45nm
Process corners	tt, ss, fs, sf in some plots
Monte Carlo samples	350
Inter-HD comparison basis	$$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$4 or $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$5 challenges across dies

Intra-HD is measured by re-sampling under perturbed temperature and voltage, while inter-HD is obtained by comparing challenges across dies. The paper also states that process variations are included in the comparison between CMOS-based and memristor-based Arbiter PUFs. Taken together, this setup frames the Stanford model not merely as an isolated device model but as a statistical source of PUF entropy and stability within a hybrid CMOS-memory implementation.

6. Reported results, scope, and limitations

The principal reported result is that memristor-based PUFs offer better reliability than CMOS-based designs, although uniqueness needs further improvement (Rahman et al., 6 Jul 2025). In Monte Carlo simulations with 350 runs, the paper reports up to 99.38 % reliability and 12–50 % uniqueness depending on the number of response bits. The study therefore presents a favorable reliability outcome while simultaneously identifying a limitation in uniqueness.

The paper also states that its sole model-level change relative to earlier PUF designs is to replace the simpler Biolek memristor model by the Stanford model. It does not alter Li et al.’s equations in any fundamental way; only the parameters $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$6 are chosen to match a 10 nm TiN/HfOₓ/TiOₓ/Pt RRAM device. This constrains the scope of the contribution: the novelty lies in device-model substitution within a PUF analysis flow rather than in a new memristor theory.

An objective reading of the reported results suggests a trade-off. The stochastic filament evolution represented by $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$7 and $$\frac{dg}{dt} \;=\; f_g\bigl(V,g,r\bigr)\;+\;\delta g\,\chi(t) \quad,\quad \frac{dr}{dt} \;=\; f_r\bigl(V,g,r\bigr)\;+\;\delta r\,\chi(t) .$$8 is used to improve security-relevant randomness, but the measured uniqueness range indicates that increasing physically grounded stochasticity does not automatically produce ideal inter-chip separation. The paper accordingly characterizes the design as reasonable for secure applications in hardware security while noting that uniqueness requires further improvement. This is also a useful corrective to a common simplification in PUF discussions: stochastic switching alone is not presented as sufficient; it must be evaluated jointly through inter-HD and intra-HD under temperature, voltage, and process variations.