Scalable Fluxonium Processor Architecture

• The paper presents scalable fluxonium processor architectures that preserve fluxonium’s strong anharmonicity and long coherence while integrating various modular designs.
• It compares architectural families—such as 2D lattices, modular FTF cells, and frequency-partitioned DTC layouts—to optimize spectral separation and minimize unwanted crosstalk.
• Gate strategies, including microwave-activated CZ, iSWAP, and native multi-qubit phases, achieve high-fidelity fast operations while simplifying reset and control for error correction.

Scalable fluxonium processor architecture denotes the family of superconducting-processor designs that seek to preserve fluxonium’s strong anharmonicity and long coherence while extending it to many-qubit lattices, parallel control, and error-correction workloads. In recent work, this has come to include compact 2D square lattices, modular fluxonium–transmon–fluxonium unit cells, alternating fluxonium–transmon lattices, double-transmon and low-shunt-capacitance couplers, and centimeter-scale long-range interconnects. Across these variants, the recurring architectural principle is the same: computational states are kept nearly decoupled at idle, while non-computational manifolds or engineered coupler excitations are activated only when gates, reset, or readout require them (Nguyen et al., 2022, Zhan et al., 15 Apr 2026, Chan et al., 29 Apr 2026, Zhao et al., 14 Apr 2026).

1. Architectural families and their common objectives

The literature does not present a single canonical scalable fluxonium processor. Instead, several closely related architectural lines have emerged. One line uses a 2D square lattice of compact high-coherence fluxoniums with individual resonators, a shared readout bus, diplexed RF/DC control, and multi-path qubit–qubit coupling chosen to cancel static $ZZ$ (Nguyen et al., 2022). A second line centers on the modular fluxonium–transmon–fluxonium, or FTF, unit cell, in which a tunable transmon coupler mediates nearest-neighbor interactions; this line has advanced from small-system gate studies to a 22-qubit chain with 21 couplers and parallel operations (Zhan et al., 15 Apr 2026). A third line uses a frequency-partitioned architecture with a double-transmon coupler, or DTC, to combine strong interaction, large qubit spacing, fast reset, and dispersive readout in a single system-level design workflow (Chan et al., 29 Apr 2026). Additional variants include alternating fluxonium–transmon lattices aimed at error-corrected processors (Heunisch et al., 12 Aug 2025), low-shunt-capacitance couplers for dense 2D connectivity (Zhao et al., 1 Jun 2026), long-range tunable couplers for modular chiplet-scale interconnects beyond one centimeter (Zhao et al., 14 Apr 2026), and fixed-frequency square-grid schemes with all-microwave gates (Kugut et al., 24 Dec 2025).

Despite these differences, the design objectives are highly consistent. Architectures seek low residual $ZZ$ and $XX$, high on/off interaction contrast, compatibility with dispersive readout, manageable capacitance loading, and a frequency plan that separates computational, plasmon, coupler, reset, and readout bands. They also seek a local control model: interactions should be activated on one edge or one star-shaped neighborhood without introducing large spectator shifts elsewhere in the lattice (Zhan et al., 15 Apr 2026, 2504.09888).

2. Fluxonium operating regime, spectral structure, and manufacturability

The fundamental device model is the fluxonium Hamiltonian

$$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$

with charging, inductive, and Josephson energies $E_C$, $E_L$, and $E_J$ (Zhao et al., 25 Jul 2025, Nguyen et al., 2022). In the standard half-flux operating regime, $\phi_{\mathrm{ext}}=\pi$, the potential is symmetric and the eigenstates have definite parity. This suppresses the charge-dipole matrix element of the computational $|0\rangle \leftrightarrow |1\rangle$ transition relative to the plasmon $|1\rangle \leftrightarrow |2\rangle$ transition, so the computational manifold can remain weakly coupled while non-computational manifolds retain transmon-like dipoles (Zhao et al., 25 Jul 2025). In the tunable-coupler architectures, fluxonium computational transitions typically lie in the $ZZ$0–$ZZ$1 MHz range, while noncomputational plasmon transitions $ZZ$2 fall at $ZZ$3–$ZZ$4 GHz and $ZZ$5 near $ZZ$6–$ZZ$7 GHz; coupler and readout bands are then placed above or between these ranges to maintain spectral partitioning (Zhan et al., 15 Apr 2026). An alternative branch, integer fluxonium, operates at the zero-flux sweet spot with qubit frequencies in the $ZZ$8–$ZZ$9 GHz range, retaining first-order flux-noise protection while easing some low-frequency control constraints (Wang et al., 5 Sep 2025).

This spectral separation is the basis for most scalable designs. Readout resonators are deliberately placed well above the computational band, reset resonators are placed between $XX$0 and $XX$1 or below $XX$2 at a different bias point, and tunable couplers are arranged so that idle detunings are large while gate biases bring the relevant coupler mode close to plasmon transitions (Chan et al., 29 Apr 2026). In the DTC framework, for example, an optimized tile uses $XX$3 GHz for reset, $XX$4 GHz for the fluxonium plasmon, $XX$5 GHz for the DTC off mode, and $XX$6 GHz for readout, so that gate, reset, and readout functions occupy non-overlapping spectral regions (Chan et al., 29 Apr 2026).

Scalability also depends on whether these parameters can be manufactured reproducibly. Wafer-scale overlap-junction processing has been reported with nearly $XX$7 yield across a 2-inch sapphire wafer, less than $XX$8 relative standard deviation for the phase-slip junction, less than $XX$9 for the entire junction-array superinductor, and energy-relaxation times exceeding $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$0 millisecond at the flux frustration point (Wang et al., 2024). The same work argues that such uniformity supports deterministic frequency allocation and reduced per-qubit calibration overhead in large fluxonium arrays (Wang et al., 2024).

3. Couplers, idle-state engineering, and suppression of unwanted interactions

The central architectural question is how to couple many fluxoniums strongly enough for fast gates without introducing large always-on interactions. In the experimentally validated FTF approach, each fluxonium pair is linked by a transmon-based tunable coupler. In the 22-qubit chain realization, the coupler sits above $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$1 GHz in the coupling-OFF configuration and is flux-tuned into the $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$2–$$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$3 GHz band for the coupling-ON configuration, where it hybridizes with the fluxonium plasmon manifold (Zhan et al., 15 Apr 2026). Because the OFF state is set by large detuning from the plasmon transitions, rather than by delicate cancellation of direct and mediated paths, measured residual $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$4 is below $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$5 kHz for all adjacent pairs in both OFF and ON bias configurations, residual $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$6 is below $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$7 kHz, and spectator-induced frequency shifts remain below $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$8 kHz when the intermediate coupler is OFF (Zhan et al., 15 Apr 2026).

Several proposals generalize this logic. The DTC architecture replaces the single transmon with two coupled transmons whose common and differential modes interfere destructively at a tunable turn-off point. In the optimized regime, $$H = 4E_C n^2 + \frac{1}{2}E_L(\phi-\phi_{\mathrm{ext}})^2 - E_J\cos\phi,$$9 GHz, and the spectator-conditioned crosstalk metric satisfies $E_C$0 kHz across $E_C$1 of 100 disorder samples (Chan et al., 29 Apr 2026). Low-shunt-capacitance couplers attack a different bottleneck: capacitance loading. With $E_C$2 fF, coupling capacitances $E_C$3 in the $E_C$4–$E_C$5 fF range are sufficient for strong tunable interactions, preserving the qubit capacitance budget needed for four-neighbor connectivity in a square lattice; in the reported examples, computational $E_C$6 remains below $E_C$7 kHz across all biases (Zhao et al., 1 Jun 2026). For modular processors, the long-range tunable coupler, or LTC, uses two $E_C$8 coplanar-waveguide resonators linked by an rf-SQUID-mediated inductive coupler. Its OFF point is intrinsic to the coupler, not the qubits, and at the qubit level the residual conditional shifts at OFF are below $E_C$9 kHz while ON-state shifts are in the tens of MHz (Zhao et al., 14 Apr 2026).

A broader lesson is that suppressing computational $E_L$0 is necessary but not sufficient. Recent analyses emphasize that always-on interactions among non-computational states can degrade initialization, control, and readout even when $E_L$1 is already small (2504.09888). That work identifies state-dependent plasmon shifts

$E_L$2

as a second crosstalk channel that must be nulled at idle, and proposes tunable plasmon couplers precisely to make spectators electromagnetically silent outside active gates (2504.09888). This directly addresses a common misconception inherited from transmon practice: in fluxonium lattices, static $E_L$3 is not the only architectural interaction that must be engineered away.

4. Gate mechanisms: from two-qubit CZ to native multi-qubit phases

The mature gate families in scalable fluxonium architectures are now diverse. In the 22-qubit FTF processor, the microwave-activated CZ gate uses a flux pulse that parks the transmon coupler near $E_L$4 and a cosine-enveloped microwave pulse on the coupler, yielding a best interleaved randomized-benchmarking CZ fidelity of $E_L$5 at an optimized duration of $E_L$6 ns, with an average CZ fidelity in repeated trials of $E_L$7 (Zhan et al., 15 Apr 2026). Earlier fluxonium processors based on direct capacitive coupling had already demonstrated an iSWAP gate of $E_L$8 ns with fidelity up to $E_L$9, showing that fluxonium can support fast entangling operations even without the newer tunable-coupler machinery (Bao et al., 2021).

A distinctive fluxonium development is the use of non-computational manifolds to realize native many-body gates. In architectures with tunable plasmon interactions, selective driving of $E_J$0 on a central qubit conditioned on the states of its neighbors implements native $E_J$1 operations. The reported case studies give CCZ, CCCZ, and CCCCZ gate lengths of approximately $E_J$2, $E_J$3, and $E_J$4, with errors of approximately $E_J$5, respectively (Zhao et al., 25 Jul 2025). The same work gives a high-fidelity baseline CZ of $E_J$6–$E_J$7 ns with error $E_J$8–$E_J$9, and explicitly argues that the architecture remains compatible with existing single- and two-qubit gate realizations (Zhao et al., 25 Jul 2025).

Other proposals optimize different tradeoffs. In an all-microwave square-grid design with fixed-frequency transmon couplers, calibrated coupler drives realize $\phi_{\mathrm{ext}}=\pi$0 ns CZ gates with coherent errors below $\phi_{\mathrm{ext}}=\pi$1, and $\phi_{\mathrm{ext}}=\pi$2 ns CZZ gates that reduce incoherent error by $\phi_{\mathrm{ext}}=\pi$3 compared with two sequential CZs sharing a common qubit (Kugut et al., 24 Dec 2025). Integer-fluxonium FTF architectures report both a flux-activated adiabatic CZ and a microwave-activated non-adiabatic CZ, each with coherent error on the order of $\phi_{\mathrm{ext}}=\pi$4 within gate durations of several tens of nanoseconds (Wang et al., 5 Sep 2025). The long-range modular LTC similarly targets sub-100-ns inter-module CZ with intrinsic error below $\phi_{\mathrm{ext}}=\pi$5, indicating that modularity need not imply a qualitatively slower gate layer (Zhao et al., 14 Apr 2026).

These results collectively indicate that scalable fluxonium architectures no longer depend on a single entangling primitive. The operative distinction is instead between gate activation channels: computational-subspace exchange, plasmon-mediated conditional shifts, coupler-level geometric phases, and native multi-control phases all appear in the literature. This suggests that fluxonium scaling is increasingly a question of choosing the gate family that best matches the coupler physics and spectral budget of a given processor.

5. Readout, reset, control, and packaging as architectural subsystems

Scalable fluxonium processors require a readout and reset layer that is compatible with low qubit frequencies and strong anharmonicity. Dispersive readout remains the standard approach, but several system-level variants have been demonstrated. In a tantalum-based high-coherence fluxonium qubit, single-shot assignment fidelity reaches $\phi_{\mathrm{ext}}=\pi$6 without and $\phi_{\mathrm{ext}}=\pi$7 with a Josephson Parametric Amplifier, while the QND repeatability fidelity is $\phi_{\mathrm{ext}}=\pi$8 (Bothara et al., 28 Jan 2025). In the common-bus architecture, four resonators couple capacitively to one superconducting bus for multiplexed readout, with $\phi_{\mathrm{ext}}=\pi$9 MHz over a broad resonator band and no Purcell filters required in the proposed design (Nguyen et al., 2022). Flip-chip multi-chip packaging extends this logic to a modular hardware stack: a quantum chip carrying four uncoupled fluxoniums is bump-bonded to a carrier chip with one shared feedline, four microwave drive lines, and four DC flux lines, and measured flux-bias crosstalk is negligible (Somoroff et al., 2023).

Reset is a particularly important subsystem because low-frequency fluxoniums can have significant thermal excited-state occupation. Several fast-reset mechanisms have now been integrated into scalable architectural proposals. A symmetry-broken single-tone sideband protocol exceeds $|0\rangle \leftrightarrow |1\rangle$0 initialization fidelity within a duration of $|0\rangle \leftrightarrow |1\rangle$1 ns and simultaneously removes second-excited-state population, which is especially relevant for leakage management in many-qubit cycles (Wang et al., 2024). A unified flux-control architecture collapses both transverse and longitudinal single-qubit control onto one filtered flux line, preserves coherence times above $|0\rangle \leftrightarrow |1\rangle$2s, enables active reset with approximately $|0\rangle \leftrightarrow |1\rangle$3 fidelity, and reaches $|0\rangle \leftrightarrow |1\rangle$4-ns single-qubit gates with fidelities exceeding $|0\rangle \leftrightarrow |1\rangle$5 from the same channel (Pan et al., 25 May 2026). More conventional active reset based on a readout resonator damping channel had already yielded $|0\rangle \leftrightarrow |1\rangle$6 ground-state population in earlier fluxonium processors (Bao et al., 2021).

Control simplification is therefore an increasingly visible architectural theme. Low-frequency operation allows direct arbitrary-waveform-generator synthesis without the mixer and local-oscillator infrastructure standard in transmon systems (Nguyen et al., 2022). Unified flux control reduces control hardware overhead by roughly a factor of $|0\rangle \leftrightarrow |1\rangle$7 per qubit, while FPGA-native waveform synthesis compresses long sequences into short reusable pulse primitives (Pan et al., 25 May 2026). For scalability, these developments matter as much as the entangling gates themselves, because cryogenic line count, filtering, and calibration overhead are often the first system bottlenecks to appear as arrays grow.

6. Demonstrations, quantum-error-correction relevance, and unresolved challenges

The strongest evidence that scalable fluxonium architecture is more than a design proposal comes from many-qubit demonstrations. The 22-qubit FTF processor validates a repeated unit cell in a long chain, supports parallel single- and two-qubit operations, and deterministically generates Greenberger–Horne–Zeilinger states involving up to 10 qubits. In that device, parallel single-qubit fidelities approach $|0\rangle \leftrightarrow |1\rangle$8, the best CZ fidelity reaches $|0\rangle \leftrightarrow |1\rangle$9 at $|1\rangle \leftrightarrow |2\rangle$0 ns, and the 10-qubit GHZ experiment reports $|1\rangle \leftrightarrow |2\rangle$1, crossing the genuine multipartite-entanglement threshold (Zhan et al., 15 Apr 2026). Earlier system studies had already projected near-unity frequency-allocation yield for thousands of qubits under realistic fabrication spreads and estimated operation below threshold for the XZZX surface code with two-qubit CZ errors in the $|1\rangle \leftrightarrow |2\rangle$2–$|1\rangle \leftrightarrow |2\rangle$3 range (Nguyen et al., 2022).

Quantum-error-correction applications are now explicit design targets rather than generic motivations. Native $|1\rangle \leftrightarrow |2\rangle$4 gates allow direct multi-qubit parity phase accumulation; for a 4-body stabilizer, a single CCCCZ can replace a decomposition into at least $|1\rangle \leftrightarrow |2\rangle$5–$|1\rangle \leftrightarrow |2\rangle$6 CZs, reducing circuit depth and idle exposure (Zhao et al., 25 Jul 2025). Alternating fluxonium–transmon lattices assign fluxoniums as data qubits and fixed-frequency transmons as measurement ancillas, mapping naturally onto surface-code or heavy-hex layouts (Heunisch et al., 12 Aug 2025). In dual-species FTF triads, sequential cross-resonance gates through the central transmon yield parity checks with fidelity exceeding $|1\rangle \leftrightarrow |2\rangle$7 and logical fluxonium–fluxonium CNOT gates exceeding $|1\rangle \leftrightarrow |2\rangle$8, while only the central transmon needs direct readout (Dimitrov et al., 9 Sep 2025). For modular QEC layouts, the LTC supports degree-4 surface-code boundaries as well as degree-5 and degree-6 graphs for qLDPC codes (Zhao et al., 14 Apr 2026).

At the same time, the open problems are sharply defined. Numerical scaling studies show that trivial extrapolation of small FTF systems can fail badly: if all couplers remain effectively “on” and coupling strengths are too large, spectator-induced detunings push average two-qubit fidelity below $|1\rangle \leftrightarrow |2\rangle$9 (Zwanenburg et al., 10 Mar 2026). The same work shows that reducing $ZZ$00 to $ZZ$01 MHz, parking idle couplers about $ZZ$02 MHz above the fluxonium $ZZ$03 band, and using a fluxonium-driven CZ with DRAG and a weak compensation drive can bring averaged spectator errors below $ZZ$04 in 2D layouts (Zwanenburg et al., 10 Mar 2026). Native multi-qubit gate proposals show a second scaling limit: as the neighborhood size $ZZ$05 grows, the minimum unwanted-transition detuning shrinks, so errors become dominated by unwanted conditional phases rather than leakage (Zhao et al., 25 Jul 2025). Coherence nonuniformity across wafers, flux-control density, 2D wiring, thermal excited-state population, and measurement-induced state mixing remain live constraints even in the best current architectures (Zhan et al., 15 Apr 2026, Bothara et al., 28 Jan 2025).

The resulting picture is neither that fluxonium scalability is solved nor that it remains hypothetical. Rather, current work has established a coherent architectural program: manufacturable high-coherence qubits, explicit off-state engineering, multiple fast gate mechanisms, practical reset and readout subsystems, and first many-qubit demonstrations all now exist. This suggests that the remaining barriers are increasingly system-engineering problems—frequency planning, spectator management, packaging, calibration automation, and disorder tolerance—rather than the absence of a viable fluxonium processor architecture.